A Scalable Priority Queue Architecture for High Speed Network Processing

Zhuang, Xin; Pande, Santosh

doi:10.1109/infocom.2006.137

Cited by 22 publications

(11 citation statements)

References 32 publications

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“…Moreover, real‐time networking systems for the provision of multimedia services show obvious burstiness over several time scales as investigated by Mavromoustakis et al . and Zhuang and Pande . According to the stochastic modelling of the data transferred, the traffic can be expressed in time, exploiting fractal‐like characteristics .…”

Section: Related Work and Research Motivationmentioning

confidence: 99%

“…Several measures, which are extracted in real time, by exploiting realistic data traffic [21,15] have presented that the impact of the routing scheme responsiveness, in terms of the end-to-end transmission reliability, is important. Moreover, real-time networking systems for the provision of multimedia services show obvious burstiness over several time scales as investigated by Mavromoustakis et al [22] and Zhuang and Pande [23]. According to the stochastic modelling of the data transferred, the traffic can be expressed in time, exploiting fractal-like characteristics [24].…”

Section: Related Work and Research Motivationmentioning

confidence: 99%

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Energy‐efficient management using a traffic‐oriented routing scheme for cognitive radio networks

et al. 2015

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SUMMARYThis paper elaborates on a traffic manipulation routing scheme that associates the moments of the traffic, targeting the maximization of the energy conservation, as well as the effective resource management of the network nodes. The energy conservation is achieved through the data flow coordination, in association with the data traffic volume and the resource exchange, between the nodes that exploit radio spectrum access in cognitive radio networking architectures. The routing scheme that is proposed in this paper interrelates the backward difference of traffic moments for each node based on a series model, together with the sleep-time period, towards reflecting this measurement to the minimization of the nodes activity durations to achieve energy conservation. The effective operation of the routing scheme is achieved by exploiting a signalling mechanism that was adopted for the proper communication of the nodes over the available radio spectrum parts, such as the television white spaces. Simulation tests were conducted towards examining the validity of the proposed routing scheme via multiple performance evaluation experiments. Simulation results have shown the offered reliability and the efficiency of the proposed traffic-aware scheme, in reference to the efficient energy consumption of the networking nodes and the minimization of the delays.

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Section: Related Work and Research Motivationmentioning

confidence: 99%

Section: Related Work and Research Motivationmentioning

confidence: 99%

Energy‐efficient management using a traffic‐oriented routing scheme for cognitive radio networks

et al. 2015

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“…The size of the priority queues discussed above is limited by the availability of on-chip memory. A hybrid priority queue system (HPQS) was proposed in Zhuang and Pande (2006), where both SRAM and DRAM was used to store large priority queues used in high speed network devices. A java-based hardware-software priority queue was proposed in Chandra and Sinnen (2010), where a shift-register-based priority queue (Moon et al, 1997) was extended by appending a software binary heap.…”

Section: Hardware Priority Queuesmentioning

confidence: 99%

Hardware-software architecture for priority queue management in real-time and embedded systems

Kumar

Vyas

Cytron

et al. 2014

IJES

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The use of hardware-based data structures for accelerating real-time and embedded system applications is limited by the scarceness of hardware resources. Being limited by the silicon area available, hardware data structures cannot scale in size as easily as their software counterparts. We assert a hardware-software co-design approach is required to elegantly overcome these limitations. In this paper, we present a hybrid priority queue architecture that includes a hardware accelerated binary heap that can also be managed in software when the queue size exceeds hardware limits. A memory mapped interface provides software with access to priority-queue structured on-chip memory, which enables quick and low overhead transitions between hardware and software management. As an application of this hybrid architecture, we present a scalable task scheduler for real-time systems that reduces scheduler processing overhead and improves timing determinism of the scheduler.

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“…For example, Crowley [2004] proposes an efficient hardware design for priority queue, which is a critical component to implementing all kinds of scheduling algorithms. In Zhuang and Pande [2006], a segmented instruction cache is shown to better support real-time workloads.…”

Section: Related Workmentioning

confidence: 99%

Compiler-Supported Thread Management for Multithreaded Network Processors

Zhuang

Pande

2011

ACM Trans. Embed. Comput. Syst.

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Traditionally, runtime management involving CPU sharing, real-time scheduling, etc., is provided by the runtime environment (typically an operating system) using hardware support such as timers and interrupts. However, due to stringent performance requirements on network processors, neither OS nor hardware mechanisms are typically feasible/available. Mapping packet processing tasks on network processors involves complex trade-offs to maximize parallelism and pipelining. Due to an increase in the size of the code store and complexity of application requirements, network processors are being programmed with heterogeneous threads that may execute code belonging to different tasks on a given micro-engine. Also, most network applications are streaming applications that are typically processed in a pipelined fashion. Thus, the tasks on different micro-engines are pipelined in such a way as to maximize the throughput. Tasks themselves could have different runtime performance demands.In this article, we focus on network processors on which hardware can only schedule threads in a roundrobin fashion and no OS assistance is provided. We show that it is very difficult and inefficient for the programmer to meet the constraints of runtime management by coding them statically. Due to the infeasibility of hardware or OS solution (even in the near future), we undertake a compiler approach.We propose a complete compiler solution to automatically insert explicit context switch (ctx) instructions provided on the network processor such that the execution of threads is better manipulated at runtime to meet their constraints. Two approaches are presented that can control programs' runtime behavior with different applicability and overheads. We show that it is feasible and also opens new application domains that would need heterogeneous thread programming. Such approaches would in general become important for multicore processors.Finally, our experiments show that the runtime constraints are enforced nearly ideally with minimal runtime degradation and small code growth.

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A Scalable Priority Queue Architecture for High Speed Network Processing

Cited by 22 publications

References 32 publications

Energy‐efficient management using a traffic‐oriented routing scheme for cognitive radio networks

Energy‐efficient management using a traffic‐oriented routing scheme for cognitive radio networks

Hardware-software architecture for priority queue management in real-time and embedded systems

Compiler-Supported Thread Management for Multithreaded Network Processors

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