A SPICE model of p‐channel silicon tunneling field‐effect transistors for logic applications

Abstract

In this study, we propose a SPICE model of p-channel silicon tunneling fieldeffect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at V DD as low as 0.3 V and that c-TFET logic gates based on our model can operate 1000 times higher frequency than conventional TFET logic gates.