A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks

Abstract

Scan design is a widely used design-for-test methodology since it enhances the controllability and observability of integrated circuits significantly. However, it may become a channel to leak secret information and, hence, threatens the hardware security seriously. In this paper, a secure scan test scheme is presented to thwart all the existing scan-based noninvasive attacks. On one hand, the proposed scheme keeps isolating the cipher key when the crypto chip runs in the test mode. In this period, the data shifted out from scan chains are not related to the cipher key. On the other hand, if the crypto chip first enters the functional mode after power-ON or reset, the switching from the functional mode to the test mode is prohibited. Consequently, the intermediate sensitive data stored in scan chains are protected. The presented scheme allows performing all sorts of tests, such as stuck-at test and delay test with a simple modification, and it maintains the advantages of scan design. Furthermore, it incurs minimal area overhead while protecting powerfully a crypto chip. INDEX TERMS Advanced encryption standard (AES), hardware security, scan design, scan-based attack, testability.

Enhancing Sensor Network Security with Improved Internal Hardware Design

“…The proposed technique is also compared with other countermeasures resisting scan attacks, including MKR [22], secure DFT [33], SOSD [37] and DOS [40] in Table 4. SOSD-64 and SOSD-128 refer to the SOSD design in [37] with 64-bit and 128-bit shift register (SR), respectively.…”

“…Table 5 gives comprehensive comparison with other secure scan techniques on performances except hardware overhead. Similar with the proposed technique, MKR [22], mode reset [31], smart controller [32] and secure DFT [33] are countermeasures based secure test control. All these countermeasures have connatural resistance to brute force and do not need extra test cycles.…”

“…Recently such architecture has been proved not unassailable [29,30]. Enhancing the security of a chip has become one of main concerns to industry, and a variety of countermeasures have been developed, mainly including the following five categories:Protection of mode switching: By introducing the test controller, the values of the scan flip-flops will be reset once switch from functional mode to test mode is requested [31,32,33]. However, this countermeasure is solely applicable for mode-switching attacks and powerless to test-mode-only attacks.Blocking of encryption key: In reference [22], secure scan architecture including MKRs (Mirror Key Registers) is utilized.…”

“…Protection of mode switching: By introducing the test controller, the values of the scan flip-flops will be reset once switch from functional mode to test mode is requested [31,32,33]. However, this countermeasure is solely applicable for mode-switching attacks and powerless to test-mode-only attacks.…”

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

“…The design can jump to the secure mode from the insecure mode, however, the opposite jump is prohibited. In [29], the authors disable completely the switch between the test mode and normal mode and protect the cipher key in test mode. This can be reshuffled only after the system reset.…”