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Scan design is a widely used design-for-test methodology since it enhances the controllability and observability of integrated circuits significantly. However, it may become a channel to leak secret information and, hence, threatens the hardware security seriously. In this paper, a secure scan test scheme is presented to thwart all the existing scan-based noninvasive attacks. On one hand, the proposed scheme keeps isolating the cipher key when the crypto chip runs in the test mode. In this period, the data shifted out from scan chains are not related to the cipher key. On the other hand, if the crypto chip first enters the functional mode after power-ON or reset, the switching from the functional mode to the test mode is prohibited. Consequently, the intermediate sensitive data stored in scan chains are protected. The presented scheme allows performing all sorts of tests, such as stuck-at test and delay test with a simple modification, and it maintains the advantages of scan design. Furthermore, it incurs minimal area overhead while protecting powerfully a crypto chip. INDEX TERMS Advanced encryption standard (AES), hardware security, scan design, scan-based attack, testability.

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