2012
DOI: 10.1109/tvlsi.2010.2089071
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A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

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Cited by 62 publications
(31 citation statements)
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“…Mode-reset countermeasure [34] ScanSAT-vulnerable BIST [36] , scan on-chip comparison [43]/compaction [44], Secure test wrapper (STW) [45] ScanSAT-resilient Scan interface encryption [37] ScanSAT-resilient…”
Section: Comparison Against Nsaa [24]mentioning
confidence: 99%
“…Mode-reset countermeasure [34] ScanSAT-vulnerable BIST [36] , scan on-chip comparison [43]/compaction [44], Secure test wrapper (STW) [45] ScanSAT-resilient Scan interface encryption [37] ScanSAT-resilient…”
Section: Comparison Against Nsaa [24]mentioning
confidence: 99%
“…Weak authentication schemes involve a static secret (password) that is presented to the chip [15], [16], [17], [18], [19], [20]: To access a protected instrument i ∈ I P , the secret k i is directly applied to dedicated primary inputs [15], embedded at constant [16], [18] or variable [20] positions in scan data (scan-in bit sequence), or written to a dedicated data register in a 1149.1 circuitry [17] or an IEEE Std 1500 wrapper [19]. Since the secrets are distributed to all authorized entities and transported to the chip in plaintext, the probability that such protection schemes are eventually compromised by secret leakage is usually too large for systems with security requirements.…”
Section: Problem Formulation and Related Workmentioning
confidence: 99%
“…Other countermeasures are based on test locking mechanisms. The so-called secure test wrappers guarantee that only authorized users can unlock the test access with a password [13] or through a secure protocol [14] [15]. In addition to the area and test time overhead introduced with these solutions, a key management is required to share the test session keys with authorized users.…”
Section: Introductionmentioning
confidence: 99%