A Self‐aligned, Trilayer, a‐Si:H Thin Film Transistor Prepared from Two Photomasks

Kuo, Yue

doi:10.1149/1.2069366

Cited by 16 publications

(5 citation statements)

References 8 publications

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“…32 32 We then structured source/drain electrodes, SiO 2 passivation layer, and indium-tin oxide (ITO) transparent pixel electrodes. As a final step, the device was thermally annealed at 320 • C for 90 min.…”

Section: Methodsmentioning

confidence: 99%

“…TFT Device fabrications.-The TFT architecture in our work was an inverted staggered tri-layer structure similar to that in Ref. 32.…”

Section: Methodsmentioning

confidence: 99%

“…As an etch stopper layer, a 200 nm thick SiO 2 layer was deposited by PECVD at 250 • C and defined by dry etching. 32 We then structured source/drain electrodes, SiO 2 passivation layer, and indium-tin oxide (ITO) transparent pixel electrodes. As a final step, the device was thermally annealed at 320 • C for 90 min.…”

Section: Methodsmentioning

confidence: 99%

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Advanced Cu Interconnection via Electroless-Plated Ni Interlayer on the Gate of Oxide Thin-Film Transistors

Nam

Moon²,

Lee³

et al. 2014

ECS J. Solid State Sci. Technol.

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We demonstrate Cu interconnection/electrode formation in bottom gate InGaZnO (IGZO) thin-film transistors (TFTs), so that conductivity may be enhanced and a more advanced display panel may replace conventional Al and Mo. To date, the development of a Cu interconnection/electrode has been hampered by the poor adhesion between Cu and SiO 2 , the main gate insulator (GI) for IGZO TFTs. However, our research shows that an electro-less selective plating of Na-free Ni on pre-patterned Cu electrodes can make this goal obtainable. According to the bias-and photo-stability measurements, our IGZO TFT with Na-free Ni-plated Cu electrodes are much more stable than IGZO TFTs prepared with conventional methods such as NaOH-induced Ni plating on Cu and H-containing SiN x /SiO 2 double layer GI on Cu. Moreover, the conventionally-prepared devices were also photo-sensitive due to the Na or H ions diffused into the GI/channel interface area. We conclude that electro-less plating of Na-free Ni on Cu is a promising approach for advanced future display panel by oxide TFTs.Until recently, amorphous (a)-Si based thin-film transistor (TFT) has led the liquid crystal display (LCD) industry due to its superior uniformity at large scale. However, the more developed display industry is now demanding higher performance and resolution than available in general a-Si TFTs. High-performance TFT-LCD and active matrix organic light-emitting diodes (AMOLEDs) are now being fabricated with low-temperature poly-Si (LTPS) TFT technology, which has limitations in large-scale displays in addition to process complexity and cost. As an alternative to such Si-based TFTs, amorphous oxide semiconductor TFTs have recently attracted much attention due to their mobility, operational stability, and simple fabrication process.

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Section: Methodsmentioning

confidence: 99%

“…TFT Device fabrications.-The TFT architecture in our work was an inverted staggered tri-layer structure similar to that in Ref. 32.…”

Section: Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Advanced Cu Interconnection via Electroless-Plated Ni Interlayer on the Gate of Oxide Thin-Film Transistors

Nam

Moon²,

Lee³

et al. 2014

ECS J. Solid State Sci. Technol.

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“…• Complete self-aligned, inverted, staggered tri-layer TFT fabricated using 2 photomasks with large process windows and excellent device characteristics (39,40). • Vertically redundant, horizontally redundant, or multi-channel TFT structures with improved on-current or negligible photosensitivity demonstrated (41,42,43).…”

Section: Structuresmentioning

confidence: 99%

ELECTRONICS AND PHOTONICS DIVISION AWARD ADDRESS: Thin Film Transistor and ULSIC Technologies - Parallel or Crossing?

Kuo

2007

ECS Trans.

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In the last 2 decades, the thin film transistor (TFT) technology has advanced dramatically accompanied with extraordinary growth of market. In this paper, the author compared the history of TFTs and ULSIC as well as their markets. The unique material, process, and device properties of the a-Si:H TFT was responsible for its current success and established the foundation for developments beyond liquid crystal displays (LCDs). Due to different device characters and limits, TFTs and ULSIC have separate application areas. However, they can be properly integrated to create new functions and products. The knowledge obtained from the large- area TFT array studies can help ULSIC migration to 15-inch wafers.

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“…Since very thin -Si:H layers can improve TFT extrinsic mobility [4], thicker -Si:H layers constrain the self-aligned BCE-TFT performance. To achieve self-alignment for high-performance TFT's, fully self-aligned tri-layer TFT processes have also been demonstrated which use either an ion shower doping step [5], or an extra dataalignment photolithography step [6]. While the former results in a minimum channel length determined only by the minimum gate dimension, and the increased performance associated with tri-layer devices, it requires an ion doping process which has not been used in AMLCD manufacturing, and is not commercially available for very large area applications.…”

Section: Introductionmentioning

confidence: 99%

Fully self-aligned tri-layer a-Si:H thin-film transistors with deposited doped contact layer

Thomasson

Jackson

1998

IEEE Electron Device Lett.

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We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFT's with deposited n + contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFT's. We have fabricated fully self-aligned tri-layer a-Si:H TFT's with excellent device performance, and contact overlaps <1 m. For a 20-m channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V DS = 0:1 V) and saturation region (V DS = 25 V) extrinsic mobility values are both 1.2 cm 2 /V-s, the off currents are <1 pA, and the on/off current ratio is >10 7 :

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A Self‐aligned, Trilayer, a‐Si:H Thin Film Transistor Prepared from Two Photomasks

Cited by 16 publications

References 8 publications

Advanced Cu Interconnection via Electroless-Plated Ni Interlayer on the Gate of Oxide Thin-Film Transistors

Advanced Cu Interconnection via Electroless-Plated Ni Interlayer on the Gate of Oxide Thin-Film Transistors

ELECTRONICS AND PHOTONICS DIVISION AWARD ADDRESS: Thin Film Transistor and ULSIC Technologies - Parallel or Crossing?

Fully self-aligned tri-layer a-Si:H thin-film transistors with deposited doped contact layer

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