A self-reconfiguration architecture for mesh arrays

Abstract

Recent advances in V L S I technologv has stimulated research in mussively parallel computers to satisJv the continuousl? increasing demand for computer power in advanced science and technology applications. Mesh-intercortnection is one of the most attractive interconnections and architectures for massively parallel computers. This puper addresses a new reconjlgurable architecture to implement massively parullel meshurruys on a silicon wafer by wafer scale integration ( W S I I , which is expected as U promising technology to construct mussively parallel computers on silicon wafers. The performance of the proposed scheme is discussed with respect to system yield. It is confrmed that the reconfigurable architecture without global information on the fault distribution achieves the same system yield as the eurlier designs based on U gruph theoty which requires on the grobal information.