Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement

Takanami, Itsuo

doi:10.1109/dftvs.2001.966762

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…For local reconfiguration [1][2][3][4][5][6][7][8], spare nodes are evenly distributed in the mesh network. Each spare node connects only to its neighboring regular nodes--no interconnection between spare nodes is allowed.…”

Section: Local Reconfigurationmentioning

confidence: 99%

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An efficient reconfiguration scheme for fault-tolerant meshes

Chuang

Yao

2005

Information Sciences

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Section: Local Reconfigurationmentioning

confidence: 99%

“…Similar researches have been conducted for various architectures, such as hypercubes, trees, meshes and k-ary ncubes [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. These designs employ either local or global reconfiguration in their replacement operations.…”

Section: Introductionmentioning

confidence: 97%

An efficient reconfiguration scheme for fault-tolerant meshes

Chuang

Yao

2005

Information Sciences

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“…These spare PEs are used to replace faulty elements in the reconfigurable system. Various techniques for redundancy approach have been described in [2][3][4][5][6]. However, if the system contains excessive faulty elements such that the spare elements cannot replace all the faulty ones due to the fact that the dimensionality of the arrays is fixed, the system is no longer reconfigurable and has to be discarded.…”

Section: Introductionmentioning

confidence: 99%

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays

Zhu

Lam

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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This paper presents a heuristic approach to accelerate the reconfiguration of two-dimensional degradable VLSI arrays linked by 4-port switches in presence of faulty processing elements (PEs). In particular, we proposed a technique to preprocess the host array by 1) identifying fault-free PEs that cannot form the target array due to their proximity to faulty PEs, and 2) labeling these fault-free PEs as faults. The proposed preprocessing method minimizes the number of PEs that will be considered for reconfiguration, thus accelerating the reconfiguration process. Simulation results show that the runtime of two well-known algorithms are significantly reduced by employing the preprocessing technique. In addition, we demonstrate the scalability of the proposed technique by showing that the runtime reduction rate increases with increasing fault density.I.

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Minimizing interconnect length on reconfigurable meshes

Srikanthan

Wang

2009

Front. Comput. Sci. China

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Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle ( k/2 th ) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

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Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement

Cited by 5 publications

References 7 publications

An efficient reconfiguration scheme for fault-tolerant meshes

An efficient reconfiguration scheme for fault-tolerant meshes

Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays

Minimizing interconnect length on reconfigurable meshes

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