A self-test approach using accumulators as test pattern generators

Stroele, A.P.

doi:10.1109/iscas.1995.523844

Cited by 23 publications

(11 citation statements)

References 5 publications

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“…The weight assignments for these subsets is W(S1)={-,-, 1,-,1} and W(S2)={-, -, 0, 1, 0}, where a "_" denotes a weight assignment of 0.5, a "1" indicates that the input is constantly driven by the logic "1" value, and "0" indicates that the input is driven by the logic "0" value. In the first assignment, inputs A [2] and A[0] are constantly driven by "1", while inputs A [4], A [3], A [1] are pseudo randomly generated (i.e., have weights 0.5). Similarly, in the second weight assignment (subset S2), inputs A [2] and A[0] are constantly driven by "0", input A[1] is driven by "1" and inputs A [4] and A [3] are pseudo randomly generated.…”

Section: A Accumulator-based 3-weight Pattern Generationmentioning

confidence: 99%

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Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR

Sindhu¹

2013

IOSR-JECE

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Section: A Accumulator-based 3-weight Pattern Generationmentioning

confidence: 99%

“…The arsenal of pseudorandom generators includes, among others, linear feedback shift registers(LFSRs) [1], cellular automata [2], and accumulators driven bya constant value [3]. For circuits with hard-to-detect faults, a large number of random patterns have to be generated before high fault coverage is achieved.…”

Section: Introductionmentioning

confidence: 99%

Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR

Sindhu¹

2013

IOSR-JECE

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“…Techniques for generating pseudo-random patterns and compacting test responses using simple programs have been proposed in [1,9,18,[21][22][23]. Techniques for mixed-mode BIST using embedded processors have been described in [7] and [10].…”

Section: Related Workmentioning

confidence: 99%

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Jas¹,

Touba²,

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.

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“…accumulators and counters) that very often occur in current very large scale integration (VLSI) circuits (e.g. data path architectures, digital signal processors) to generate test patterns to test one or more modules in the circuit [18,19]. The utilisation of existing modules for BIST purposes is favoured by (a) low hardware overhead, (b) low impact on the circuit normal operating speed, and (c) the fact that the modules used for BIST purposes are exercised.…”

Section: Introductionmentioning

confidence: 99%

Arithmetic module-based built-in self test architecture for two-pattern testing

Voyiatzis

Efstathiou

Antonopoulou

et al. 2012

IET Comput. Digit. Tech.

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Built-in self test (BIST) techniques use test pattern-generation and response-verification operations, reducing the need for external testing. BIST techniques that use arithmetic modules existing in the circuit (accumulators, counters etc.) to perform the testgeneration and response-verification operations have been proposed in the open literature. Two-pattern tests are exercised to detect complementary metal oxide semiconductor (CMOS) stuck-open faults and to assure correct temporal circuit operation at clock speed (delay fault testing). In this study, a novel, arithmetic module-based BIST architecture for two-pattern testing (ABAS) is presented that exercises arithmetic modules to generate two-pattern tests; the hardware overhead required by the presented scheme, provided the availability of such modules is by far the lowest of all schemes that have been presented for the same purpose in the open literature.

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A self-test approach using accumulators as test pattern generators

Cited by 23 publications

References 5 publications

Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR

Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Arithmetic module-based built-in self test architecture for two-pattern testing

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