A self-timed structural test methodology for timing anomalies due to defects and process variations

Pulse propagation for the detection of small delay defects

“…In a combinational circuit, ROPs and bridgings can be detected using a clock period smaller than that fixed by the critical path, flip-flops' timing parameters and clock skews [5,6,7]. In this way, the available slack is reduced and the transitions of the affected primary outputs may occur after the sampling instant, thus resulting in fault detection.…”

“…In order to reduce the number of data, multiple sampling times are still used in [7], but the author exploits the ordering of the transition times of the signals belonging to the logic block under test. A DF is detected if the switching order of any two outputs is opposite to that evaluated by means of fault-free simulation.…”

“…In particular, in [5] we have to match two samples of clock distribution networks belonging to neighboring dies. In [7], instead, we have to match two (partially) different clock distribution subnetworks in the same die. In this regard, it is well known that in deep-submicron devices, both within-die and die-todie timing fluctuations are expected to grow [8].…”

“…Differently from the clock signal used in [5,6,7], the input pulses are locally generated and the output pulses are locally detected, thus avoiding the problems related to the clock distribution network. This is achieved with some hardware overhead.…”

Silicon evaluation of longest path avoidance testing for small delay defects

“…In addition, hazard capture increases yield loss to unacceptable levels. Researchers have shown that Hazard-Aware testing can limit this loss when accuracy requirements are met for signal settling time estimates on target test paths [7][8] [15] [16]. Several, timing-aware test pattern generation algorithms have been proposed to increase the sensitivity of conventional transition fault tests to small-delay defects [3] [13][10] [11].…”