A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

Abstract

A shallow and deep trench isolation process module for high performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ is presented in detail. The shallow trench is etched prior to the deep trench, allowing the deep trench to be placed self-aligned to the shallow trench edge. By planarizing the polycrystalline silicon deep trench filling using chemical mechanical polishing ͑CMP͒ before etchback, the recess into deep trenches is decreased and polysilicon spacer formation at the active area edges is avoided. The poly CMP is stopped before all polysilicon in the active area is removed, to avoid polysilicon dishing and erosion of oxide on top of nitride on active area. Important issues arising during process development are discussed. Two different slurries were evaluated, which resulted in two different nonuniformities of polysilicon thickness. Nonuniformity transfers partially down to a range of recesses into the deep trenches, but the recesses were much smaller compared to the etchback only. Highdensity chemical vapor deposition was used for shallow trench filling and a direct shallow trench isolation-CMP process was developed. The feasibility of the process module was demonstrated using a 0.25 m, 200 mm bipolar double-poly rf process with optional SiGe epi base. Electrical results from completed transistors are presented to verify the function of the module.All nontrivial integrated electronics involve connecting isolated devices through specific electrical connection paths. The device isolation scheme is, therefore, one of the critical parts for integrated circuit processes. Many different schemes have been developed over the years. Parameters like minimum isolation spacing, surface planarity, defect density, process complexity, and electrical properties ͑dc and high frequency͒ influence the choice of a scheme for the particular application and process technology. Mesa isolation, junction isolation, and localized oxidation of silicon ͑LOCOS͒ are techniques in use. As feature sizes continue to decrease, there is a need to reduce shortcomings, such as low packing density, high leakage currents, and latch-up between devices, associated with older isolation technologies.In complementary metal-oxide-semiconductor ͑CMOS͒ technology, LOCOS has been replaced by shallow trench isolation ͑STI͒. 1,2 The lateral encroachment into the active area when using LOCOS, due to oxidation under the nitride at the edges, can be avoided by using STI. Thereby, the lateral control increases, tighter design rules can be applied, and parasitic capacitances are reduced. STI also offers a more planar surface and the possibility to increase the field oxide thickness.A complexity in high-performance rf bipolar complementary metal-oxide-semiconductor ͑BiCMOS͒ processes is the integration of STI with deep trench isolation ͑DTI͒. Deep trenches, usually with a depth larger than a couple of micrometers, are mainly used to isolate different devices and device groups ͑wells͒ in CMOS/ BiCMOS technology. The trenches are filled with oxide...

Influence of SOI-generated stress on BiCMOS performance

“…Processing started with subcollector formation, collector epi deposition and formation of LOCOS or STI with no changes in the process flow for the SOI wafers. The bulk wafers in the 0.25 lm process used a self-aligned STI + DTI scheme [9]. To simplify the process flow, it was decided to use the resist as a trench mask for DT.…”

Self-Heating Effects in a BiCMOS on SOI Technology for RFIC Applications

“…Processing then followed the base-line process flow, including subcollector formation, collector epi deposition and STI formation. For the bulk wafers, the self-aligned shallow and deep trench isolation, as described in [13], was used. The SOI wafers also used undoped polysilicon for the trench filling, but a resist mask was used instead of the original oxide hard mask.…”