A shallow trench isolation study for 0.25/0.18 μm CMOS technologies and beyond

Chatterjee, Amitava; Esquivel, J.; Nag, Soumya Shubhra; Ali, Iqbal; Rogers, D.; Joyner, K.; Mason, Mark E.; Mercer, Doug; Amerasekera, A.; Houston, T.W.; Chen, I.-C.

doi:10.1109/vlsit.1996.507831

Cited by 16 publications

(4 citation statements)

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“…For the first issue on burying atom switches, we introduce a highdensity plasma (HDP) SiO 2 ILD, which shows improved burying characteristics compared with a conventional plasma-CVD SiO 2 . [27][28][29][30] The surface of the HDP SiO 2 ILD burying the atom switches is successfully planarized by the following standard CMP. For the second issue on simultaneous via etching, we insert a Ta second top electrode layer on a Ru-alloy top electrode layer.…”

Section: Introductionmentioning

confidence: 99%

Logic compatible process technology for embedded atom switches in CMOS

Okamoto¹,

Tada²,

Banno³

et al. 2015

Jpn. J. Appl. Phys.

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We have developed a CMOS logic compatible process for embedding Cu atom switches in a Cu/low-k back-end-of-line without degrading interconnect and switch performance characteristics. The key technologies are (i) burying a via-interlayer dielectric layer between the switches without voids, followed by surface planarization using chemical mechanical polishing, and (ii) introducing a Ta protective second top electrode, which realizes simultaneous via-openings to both the switches and the lower interconnects without degrading physical morphology and electric properties of the switches. The developed process enables us to integrate the atom switches on logic with only two additional masks at low cost.

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Section: Introductionmentioning

confidence: 99%

Logic compatible process technology for embedded atom switches in CMOS

Okamoto¹,

Tada²,

Banno³

et al. 2015

Jpn. J. Appl. Phys.

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“…Fill insertion can potentially affect stress induced due to STI. Stress affects device characteristics because of its impact on carrier mobility and is modeled, at least in part, in today's device models (e.g., BSIMV v4.4.0) [1]. Recently STI fill insertion was noted to improve predictability of stress-induced effects and therefore reduce guardbanding [8].…”

Section: Introductionmentioning

confidence: 99%

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction

Kahng

Topaloglu

2006

2006 International Conference on Computer Design

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Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove excess of deposited oxide and attain a planar surface for successive process steps. Despite advances in STI CMP technology, pattern dependencies cause large post-CMP topography variation that can result in functional and parametric yield loss. Fill insertion is used to reduce pattern variation and consequently decrease post-CMP topography variation. Traditional fill insertion is rulebased and is used with reverse etchback to attain desired planarization quality. Due to extra costs associated with reverse etchback, "single-step" STI CMP in which fill insertion suffices is desirable.To alleviate the failures caused by imperfect CMP, we focus on two objectives for fill insertion: oxide density variation minimization and nitride density maximization. A linear programming based optimization is used to calculate oxide densities that minimize oxide density variation. Next a fill insertion methodology is presented that attains the calculated oxide density while maximizing the nitride density. Averaged over the two large testcases, the oxide density variation is reduced by 63% and minimum nitride density increased by 79% compared to tiling-based fill insertion. To assess post-CMP planarization, we run CMP simulation on the layout filled with our approach and find the planarization window (time window in which polishing can be stopped) to increase by 17% and maximum final step height (maximum difference in post-CMP oxide thickness) to decrease by 9%.

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“…For the present discussion, the leakage mechanisms are classified as being either parametric (intrinsic) or defect-related in nature. The SRAM array parametric standby leakage contributors include well isolation leakage [5], subthreshold device leakage [6], gate-oxide tunneling [7], reverse-bias diffusion leakage [8], and gate-induced drain leakage (GIDL) [9,10] for both n-FET and p-FET devices. Implant damage [11], STI stress-induced diffusion leakage [12], silicide defects [13], and contact-related defects [14] must be very carefully controlled or eliminated in order to achieve the ULP leakage obtained.…”

Section: Introductionmentioning

confidence: 99%

Ultralow-power SRAM technology

et al. 2003

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An ultralow-standby-power technology has been developed in both 0.18-m and 0.13-m lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage sixtransistor (6T) SRAM cell sizes are 4.81 m 2 and 2.34 m 2 , corresponding respectively to the 0.18-m and 0.13-m design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25ЊC and is less than 400 fA per cell at 1.5 V, 85ЊC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the wellknown gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

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A shallow trench isolation study for 0.25/0.18 μm CMOS technologies and beyond

Cited by 16 publications

References 0 publications

Logic compatible process technology for embedded atom switches in CMOS

Logic compatible process technology for embedded atom switches in CMOS

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction

Ultralow-power SRAM technology

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