Logic compatible process technology for embedded atom switches in CMOS

An atom-switch field-programmable gate array (AS-FPGA) uses a simple crossbar switch structure for signal routing. An AS-crossbar switch enables a shorter delay thanks to single-stage routing and the low capacitance of the AS, unlike a routing block which uses multi-stage multiplexers in a conventional static random access memory FPGA. However, the output of a crossbar switch has a variable load capacitance for different fan-outs when the application circuit is mapped on an AS-FPGA. The buffer driving capability for the crossbar switch needs to be carefully designed since there is a trade-off relationship between energy and delay. An optimized buffer reduces the energy–delay product (EDP) of the AS-crossbar switch by 22.3% compared with a non-optimized buffer.

Section: Introductionmentioning

confidence: 99%

An atom-switch-based field-programmable gate array with optimized driving capability buffer

Bai¹,

Miyamura²,

Nebashi³

et al. 2019

“…4,5) To overcome these issues, a nanobridge-based FPGA (NB-FPGA) has been proposed, where NBs construct highperformance compact routing matrix and memories. [6][7][8][9][10][11][12][13][14][15] The NB composed of a solid-electrolyte layer sandwiched by an active metal electrode and an inert metal electrode [16][17][18][19][20][21][22][23][24][25][26][27][28] is a nonvolatile resistance-change device, which leads to low standby power consumption. Area overhead is reduced since the NB is integrated in the backend-of-line.…”

Section: Introductionmentioning

confidence: 99%

Architecture optimization of nanobridge-based field-programmable gate array and its evaluation

Bai¹,

Sakamoto²,

Tsuji³

et al. 2017

Logic cell architecture on nanobridge-based field-programmable gate array (NB-FPGA) is investigated in terms of cell area and signal delay. Areadelay product is minimized when the cluster size is 4 and the segment length is 4, because of small area and small capacitance of nanobridge (NB). 1.34' logic density improvement and 15% energy saving, compared to the previous NB-FPGA with cluster size = 2, are demonstrated by implementing an application of a lightweight block cipher.

“…4,5) To overcome these issues, an atom-switch-based FPGA has been proposed, in which atom switches construct highperformance compact routing matrices and memories. [6][7][8][9][10][11][12][13] An atom switch composed of a solid-electrolyte layer sandwiched by an active metal electrode and an inert metal electrode [14][15][16][17][18][19][20][21][22][23][24][25] is a nonvolatile resistance-change device, which provides low standby power consumption. The area overhead is reduced owing to integration of the atom switch between 4 and 5 metals.…”

Section: Introductionmentioning

confidence: 99%

Area-efficient nonvolatile carry chain based on pass-transistor/atom-switch hybrid logic

Bai¹,

Tsuji²,

Sakamoto³

et al. 2016

Self Cite

For the first time, an area-efficient nonvolatile carry chain combining look-up tables and a pass-transistor-logic-based adder is newly developed using complementary atom switches without additional CMOS circuits. A proposed tristate switch composed of three pairs of complementary atom switches selects one of “0”, “1”, and the “carry_in” signal as the input of a common multiplexer for both a look-up table and an adder. The developed nonvolatile carry chain achieves the reductions of 20% area, 17% delay, and 17% power consumption, respectively, in comparison with a conventional nonvolatile carry chain using dedicated CMOS gates.