Area-efficient nonvolatile carry chain based on pass-transistor/atom-switch hybrid logic

Bai, Xu; Tsuji, Yoshiyuki; Sakamoto, Toshitsugu; Morioka, A.; Miyamura, Miharu; Tada, Munehiro; Banno, Naoki; Okamoto, K.; Iguchi, N.; Hada, H.

doi:10.7567/jjap.55.04ef01

Cited by 6 publications

(3 citation statements)

References 30 publications

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“…Mapping of boolean representation to PTL logic by reversing their order can achieve efficiency in terms of dynamic power dissipation due to less switching activities [10]. Power dissipation can be reduced in pass transistor technique by replacing NMOS with PMOS [11][12].…”

Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

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Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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“…4,5) To overcome these issues, an atom-switch (AS)-FPGA has been proposed in which ASs are used to construct highperformance compact routing blocks (RBs) and memories. [6][7][8][9][10][11][12][13][14][15] An AS, composed of a solid electrolyte layer sandwiched by an active metal electrode and an inert metal electrode, [16][17][18][19][20][21][22][23][24][25][26][27][28] is a non-volatile resistance-change device which leads to low standby power consumption. The area overhead is reduced because the AS is integrated in the backend of the line.…”

Section: Introductionmentioning

confidence: 99%

An atom-switch-based field-programmable gate array with optimized driving capability buffer

Bai¹,

Miyamura²,

Nebashi³

et al. 2019

Jpn. J. Appl. Phys.

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An atom-switch field-programmable gate array (AS-FPGA) uses a simple crossbar switch structure for signal routing. An AS-crossbar switch enables a shorter delay thanks to single-stage routing and the low capacitance of the AS, unlike a routing block which uses multi-stage multiplexers in a conventional static random access memory FPGA. However, the output of a crossbar switch has a variable load capacitance for different fan-outs when the application circuit is mapped on an AS-FPGA. The buffer driving capability for the crossbar switch needs to be carefully designed since there is a trade-off relationship between energy and delay. An optimized buffer reduces the energy–delay product (EDP) of the AS-crossbar switch by 22.3% compared with a non-optimized buffer.

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“…4,5) To overcome these issues, a nanobridge-based FPGA (NB-FPGA) has been proposed, where NBs construct highperformance compact routing matrix and memories. [6][7][8][9][10][11][12][13][14][15] The NB composed of a solid-electrolyte layer sandwiched by an active metal electrode and an inert metal electrode [16][17][18][19][20][21][22][23][24][25][26][27][28] is a nonvolatile resistance-change device, which leads to low standby power consumption. Area overhead is reduced since the NB is integrated in the backend-of-line.…”

Section: Introductionmentioning

confidence: 99%

Architecture optimization of nanobridge-based field-programmable gate array and its evaluation

Bai¹,

Sakamoto²,

Tsuji³

et al. 2017

Jpn. J. Appl. Phys.

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Logic cell architecture on nanobridge-based field-programmable gate array (NB-FPGA) is investigated in terms of cell area and signal delay. Areadelay product is minimized when the cluster size is 4 and the segment length is 4, because of small area and small capacitance of nanobridge (NB). 1.34' logic density improvement and 15% energy saving, compared to the previous NB-FPGA with cluster size = 2, are demonstrated by implementing an application of a lightweight block cipher.

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Area-efficient nonvolatile carry chain based on pass-transistor/atom-switch hybrid logic

Cited by 6 publications

References 30 publications

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

An atom-switch-based field-programmable gate array with optimized driving capability buffer

Architecture optimization of nanobridge-based field-programmable gate array and its evaluation

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