2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) 2013
DOI: 10.1109/iscas.2013.6571979
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A SiGe 8-channel comparator for application in a synthetic aperture radiometer

Abstract: We present a high-speed low-power 8-channel comparator tailored for the application of sampling antenna signals in a cross-correlator system for space-borne synthetic aperture radiometer instruments. Features like clock return path, perchannel offset calibration and bias current tuning make the comparator adaptable and gives the possibility to adjust the comparator for low power consumption, while keeping performance within the requirements of the cross-correlator system. The comparator has been implemented an… Show more

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Cited by 5 publications
(6 citation statements)
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“…First, it is impossible for the FPGA to do cross-correlation processing synchronous with a clock up to 1 GHz, and a mechanism like serial-to-parallel conversion is needed to reduce the working frequency without data loss. Second, common comparator chips have no source-synchronous clock output for data reception as the ASIC presented in [23], while the sampled data have to be synchronized to the same clock domain to perform cross-correlation. Third, pin variations of the FPGA will introduce non-negligible bit skew when synchronizing tens of data lines across several banks to the same clock domain at 1 GHz, even though the arriving data are totally synchronous at the input/output (IO) pins of the FPGA.…”
Section: Architecturementioning
confidence: 99%
“…First, it is impossible for the FPGA to do cross-correlation processing synchronous with a clock up to 1 GHz, and a mechanism like serial-to-parallel conversion is needed to reduce the working frequency without data loss. Second, common comparator chips have no source-synchronous clock output for data reception as the ASIC presented in [23], while the sampled data have to be synchronized to the same clock domain to perform cross-correlation. Third, pin variations of the FPGA will introduce non-negligible bit skew when synchronizing tens of data lines across several banks to the same clock domain at 1 GHz, even though the arriving data are totally synchronous at the input/output (IO) pins of the FPGA.…”
Section: Architecturementioning
confidence: 99%
“…The signal inputs are divided into 12 banks, each with 8 data and one clock input, matching the output interface of a custombuilt ADC [9]. Clock inputs are differential and use a current mode logic (CML) based termination with 100-Ω resistors to a positive voltage level, V term .…”
Section: A Data Path and System Integrationmentioning
confidence: 99%
“…2. The custom-built ADCs [9] allow for per-channel offset tuning, making this task simple. At the system level, the input signals would then have to be split into two ADCs.…”
Section: B Reconfigurabilitymentioning
confidence: 99%
“…A cross-correlator system essentially comprises A/D conversion and signal processing. We developed ASICs for A/D conversion [2] and cross-correlation [1] separately. While integration of both on a single die would have offered some advantages, there are good reasons for splitting sampling and cross-correlation into different ASICs.…”
Section: System Architecturementioning
confidence: 99%
“…Based on two types of ASICs, our cross-correlator system demonstrates that an aperture-synthesis approach can become a viable option for an Earth-observing microwave sounder in GEO. The ASICs have each been briefly reported previously [1], [2]; this article additionally provides a full system description and reports extensive chip-and system-level measurements which verify our approach.…”
Section: Introductionmentioning
confidence: 99%