A Signature‐Based Power Model for MPSoC on FPGA

Piscitelli, Roberta; Pimentel, Andy D.

doi:10.1155/2012/196984

Cited by 9 publications

(4 citation statements)

References 25 publications

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“…Another linear-based model for the dynamic power is proposed in [25], in which the switching activity from the RTlevel is utilized to estimate component power breakdowns for the FIR filter application with a fair error (10% of average error). Power models for multiprocessor SoC (MPSoC) circuit on FPGA is conducted in [26]. The technique is based on the offline extraction of the abstract profile of an application called event signatures used to estimate the average of the total power consumption.…”

Section: Neural Networkmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system's state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system's state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way. Index Terms-Data mining, design-time method, fieldprogrammable gate array (FPGA), power modeling, register transfer-level, system on chip (SoC) monitoring.

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Section: Neural Networkmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Similar to previous work, a signature-based power model for MPSoC on FPGA [14] was proposed. Today, the Open Virtual Platform by Imperas Inc. [1] uses the same level of simulation but also tackles the simulation speed problem by proposing the OVPSim simulator since processors are not ISS but use code morphing and Just-In-Time (JIT) compilation.…”

Section: S �mentioning

confidence: 96%

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri

Palomar

Moreno

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development.The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed.The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE.The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.

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“…30.5.1, recognizing separate application and architecture models. SESAME has also been extended to allow for capturing power consumption behavior and reliability behavior of MPSoC platforms [44,45,50]. The layered infrastructure of SESAME's modeling and simulation environment is shown in Fig.…”

Section: System-level Performance Modeling and Simulationmentioning

confidence: 99%

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

Stefanov

Pimentel

Nikolov

2017

Handbook of Hardware/Software Codesign

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The complexity of modern embedded systems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process from the register-transfer level (RTL) to the so-called electronic system level (ESL). However, this opens a large gap between deployed ESL models and RTL implementations of the MPSoC under design, known as the implementation gap. Therefore, in this chapter, we present the DAEDALUS methodology which the main objective is to bridge this implementation gap for the design of streaming embedded MPSoCs. DAEDALUS does so by providing an integrated and highly automated environment for application parallelization, system-level design space exploration, and system-level hardware/software synthesis and code generation.

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A Signature‐Based Power Model for MPSoC on FPGA

Cited by 9 publications

References 25 publications

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips

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