A Silicon Nanowire Ferroelectric Field‐Effect Transistor

Abstract

The end of classical scaling has become evident as manufacturing and design scaling reaches physical and economical limits. Already since many years, Moore´s law is complemented in semiconductor industry by the so-called "More-than-Moore" approach. [1] Here, a cost-effective integration of many additional functions into state-of-the-art complementary metaloxide-semiconductor (CMOS)-based technology escorts further reduction of the transistor dimension. For this purpose, alternative materials and new device concepts are being evaluated.

WITHDRAWN: Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

“…In this paper, prior to this work, several literatures were surveyed based on structural and material engineering [4][5][6][7][8][9][10][11][12][13][14]. The effect of homogeneous and heterogeneous material in tunneling junctions [15], effect of pocket intrinsic doping on single as well as multi gate tunneling FETs [16][17], effect of device performance based on various high-k materials [18], stress-strain effects in source-channel (n-channel) and drain-channel (pchannel) TJDs [19], usage of carbon nano-tubes (CNT) in tunneling FETs [20], nano-wire tunneling FETs [21], capacitive effects in modified TJD structures [22], various symmetric and asymmetric tunneling device structures has been studied to meet the earlier mentioned scaling issues and device performance factors.…”

FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors

“…In addition, charge trapping and detrapping at Si-SiO 2 interface plays an important role in degrading the memory window and it has shown that controlling the charge trapping and the resulting imprinting is necessary in order to ensure the reliability of the FeFET [28]. Recently, it has been shown in [29] that the non-perfect screening of the polarization charges may lead to a residual electric field. This counteracts the ferroelectric polarization and results in depolarization field that may degrade the memory window of FeFET devices.…”

Improved DC Performance Analysis of a Novel Asymmetric Extended Source Tunnel FET for Fast Switching Application

“…In this paper, prior to this work, several literatures were surveyed based on structural and material engineering [4][5][6][7][8][9][10][11][12][13][14]. The effect of homogeneous and heterogeneous material in tunneling junctions [15], effect of pocket intrinsic doping on single as well as multi gate tunneling FETs [16][17], effect of device performance based on various high-k materials [18], stress-strain effects in source-channel (n-channel) and drain-channel (p-channel) TJDs [19], usage of carbon nano-tubes (CNT) in tunneling FETs [20], nano-wire tunneling FETs [21], capacitive effects in modified TJD structures [22], various symmetric and asymmetric tunneling device structures has been studied to meet the earlier mentioned scaling issues and device performance factors.…”