A simple mechanism to adapt leakage-control policies to temperature

Xekalakis, Polychronis; Κεραμίδας, Γεώργιος

doi:10.1145/1077603.1077617

Cited by 12 publications

(4 citation statements)

References 22 publications

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“…Although the implementation of SSA is not limited to combining cache decay and drowsy cache, performance evaluation, presented in Section 4, was based on these two techniques. As a result, MSA is very similar to the hybrid drowsy + decay scheme deployed by them and even other researchers [Hu et al 2003;Kaxiras et al 2005;Meng et al 2005]. The difference is that MSA does not activate an additional cache block right away once a cache miss occurs, as done by the hybrid technique.…”

Section: Temperature-aware Leakage Reductionmentioning

confidence: 74%

Snug set-associative caches

Hwang

2007

ACM Trans. Archit. Code Optim.

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As transistors keep shrinking and on-chip caches keep growing, static power dissipation resulting from leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage power by turning off unused cache lines. However, they all have to pay the price of performance degradation. This paper presents a cache architecture, the snug set-associative (SSA) cache, that cuts most of static power dissipation of caches without incuring performance penalties. The SSA cache reduces leakage power by implementing the minimum set-associative scheme, which only activates the minimal numbers of ways in each cache set, while the performance losses caused by this scheme are compensated by the base-offset load/store queues. The rationale of combining these two techniques is locality: as the contents of the cache blocks in the current working set are repeatedly accessed, same addresses would be computed again and again. The SSA cache architecture can be applied to data and instruction caches to reduce leakage power without incurring performance penalties. Experimental results show that SSA can cut static power consumption of the L1 data cache by 93%, on average, for SPECint2000 benchmarks, while the execution times are reduced by 5%. Similarly, SSA can cut leakage dissipation of the L1 instruction cache by 92%, on average, and improve performance over 3%. Furthermore, when SSA is adopted for both L1 data and instruction caches, the normalized leakage of L1 data and instruction caches is lowered to 8%, on average, while still accomplishing a 2% reduction in execution times.

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Section: Temperature-aware Leakage Reductionmentioning

confidence: 74%

Snug set-associative caches

Hwang

2007

ACM Trans. Archit. Code Optim.

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“…In this paper, we investigate the use of the cache decay methodology [12][13][14] as a mechanism to defend against cache-based side channel attacks. The cache decay methodology was initially proposed for cache leakage savings [12] and pre-fetching [14].…”

Section: Introductionmentioning

confidence: 99%

Non deterministic caches: a simple and effective defense against side channel attacks

Κεραμίδας

Αντωνόπουλος

Serpanos

et al. 2008

Des Autom Embed Syst

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Side channel cryptanalysis has received significant attention lately, because it provides a low-cost and facile way to reveal the secret information held on a secure computing system. One particular type of side channel attacks, called cache-based side channel attacks, aims to deduce information about the state of a cryptographic algorithm or its key by observing the data-dependent behavior of a microprocessor's cache memory. These attacks have been proven successful and very hard to protect against. In this paper, we introduce the use of the Cache Decay approach as an aid to guard against cache-based side channel attacks. Cache Decay controls the lifetime (called decay interval) of the cache items and was initially proposed for cache power leakage savings. By randomly selecting the decay interval of the cache, we actually create caches with non-deterministic behavior in regard to their statistics. Thus, as we demonstrate, multiple runs of the same algorithm (performing on the same input) will result in different cache statistics, defending against the attacker and reinforcing the protection offered by the system. In our work, we use a cycle-based processor simulator, enhanced with the required modifications, in order to evaluate our proposal and show that our technique can be used effectively to protect against cache-based side channel attacks.

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“…Finally, some researchers [109][110][111] have also studied the effect of temperature on the power consumption and leakage policies. In [111], authors propose a thermal-aware Chapter 2.…”

Section: Reducing Energy Consumption In Cachesmentioning

confidence: 99%

Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors

Lara¹

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Current multicores face the challenge of sharing resources among the different processor cores. Two main shared resources act as major performance bottlenecks in current designs: the off-chip main memory bandwidth and the last level cache. Additionally, as the core count grows, the network on-chip is also becoming a potential performance bottleneck, since traditional designs may find scalability issues in the near future.Memory hierarchies communicated through fast interconnects are implemented in almost every current design as they reduce the number of off-chip accesses and the overall latency, respectively. Main memory, caches, and interconnection resources, together with other widely-used techniques like prefetching, help alleviate the huge memory access latencies and limit the impact of the core-memory speed gap. However, sharing these resources brings several concerns, being one of the most challenging the management of the inter-application interference. Since almost every running application needs to access to main memory, all of them are exposed to interference from other co-runners in their way to the memory controller. For this reason, making an efficient use of the available cache space, together with achieving fast and scalable interconnects, is critical to sustain the performance in current and future designs. This dissertation analyzes and addresses the most important shortcomings of two major shared resources: the Last Level Cache (LLC) and the Network on Chip (NoC).First, we study the scalability of both electrical and optical NoCs for future multicores and many-cores. To perform this study, we model optical interconnects in a cycleaccurate multicore simulation framework. A proper model is required; otherwise, important performance deviations may be observed otherwise in the evaluation results.The study reveals that, as the core count grows, the effect of distance on the end-to-end latency can negatively impact on the processor performance. In contrast, the study also shows that silicon nanophotonics are a viable solution to solve the mentioned latency problems.This dissertation is also motivated by important design concerns related to current memory hierarchies, like the oversizing of private cache space, data replication overheads,

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A simple mechanism to adapt leakage-control policies to temperature

Cited by 12 publications

References 22 publications

Snug set-associative caches

Snug set-associative caches

Non deterministic caches: a simple and effective defense against side channel attacks

Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors

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