2017
DOI: 10.1049/iet-pel.2017.0123
|View full text |Cite
|
Sign up to set email alerts
|

A simplified structure for three‐phase 4‐level inverter employing fundamental frequency switching technique

Abstract: This study describes the design and control of simplified structure of three-phase 4-level inverter. A 4-level dc-link derived from three symmetrical dc voltage supplies and two controlled switches is connected to a three-phase 3-level neutral point clamped (3-level NPC) bridge inverter. By employing the fundamental frequency switching technique, the simplified 4-level inverter can have two distinct modes of operation: 4-level and 2-level. Compared to the well-known three-phase 4-level NPC inverter, the propos… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
8
0

Year Published

2019
2019
2021
2021

Publication Types

Select...
5

Relationship

3
2

Authors

Journals

citations
Cited by 5 publications
(8 citation statements)
references
References 27 publications
0
8
0
Order By: Relevance
“…IGBT TOSHIBA GT50J325 is used as a switch to realize the proposed topology. As shown in Figure 15A, the voltage stress across switches S 1 , S 3 , and S 5 are 60, 30, and 120 V, respectively, as given in (3), (4), and (5). As the voltage magnitude of gate signals generated from dSPACE is of low voltage and not sufficient to drive the IGBTs, a gate driver circuit made up of an IC NXP 74HCNIC74 with an optocoupler A3120.…”
Section: Experimental Verificationmentioning
confidence: 99%
See 3 more Smart Citations
“…IGBT TOSHIBA GT50J325 is used as a switch to realize the proposed topology. As shown in Figure 15A, the voltage stress across switches S 1 , S 3 , and S 5 are 60, 30, and 120 V, respectively, as given in (3), (4), and (5). As the voltage magnitude of gate signals generated from dSPACE is of low voltage and not sufficient to drive the IGBTs, a gate driver circuit made up of an IC NXP 74HCNIC74 with an optocoupler A3120.…”
Section: Experimental Verificationmentioning
confidence: 99%
“…The output voltage has a peak value of 240 V, which has eight voltage steps of 30 V. The voltage stress across the switch is shown in Figure 15A,B. As shown in Figure 15A, the voltage stress across switches S 1 , S 3 , and S 5 are 60, 30, and 120 V, respectively, as given in (3), (4), and (5). Similarly, the voltage stress across switches S 7 and S 9 is 90 and 120 V, respectively, as given by (6) and (7) and shown in Figure 14B.…”
Section: Figure 15mentioning
confidence: 99%
See 2 more Smart Citations
“…To overcome these drawbacks, multi-level converters have become an attractive topology for interfacing batteries to the grid. Compared with traditional two-level topologies, multi-level topologies have several advantages, including reduced voltage stress on switches, lower power losses, and higher grid power quality [5][6][7]. These properties also make multi-level topologies appealing for use with ESSs.…”
Section: Introductionmentioning
confidence: 99%