A simulation environment for core based embedded systems

Pétrot, Frédéric; Hommais, Denis; Greiner, Alain

doi:10.1109/simsym.1997.586495

Cited by 10 publications

(8 citation statements)

References 12 publications

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“…The community now widely agree that finite state machine (fsm) is a good computation model for simulation because it can be easily understood by designers and it can be efficiently simulated. Following initial ideas of Jennings [11], many works [2,12] are focussing on the problem of improving mpsoc simulation performances by reducing the inefficiency introduced by event driven simulation. In particular, the results of [2] state that if the fsm is represented in the form of Moore-Mealy machine, the simulation kernel can produce much more efficient simulations.…”

Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

“…The idea experimented in [2,12] is the following: if all the mealy functions of all the ips are empty then there is no need for event driven simulation, a static scheduling can be performed and the simulation will run much faster. Of course, this is in general not the case but in most ips the complexity of the mealy function will be negligible compared to the operations performed in the moore and transition function.…”

Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

“…Hence, if the simulation kernel is aware of this decomposition in the simulation models it can optimise the scheduling of the different functions to execute the mealy function as rarely as possible. In SystemCass [2] the way to write the more, mealy and transition functions is precisely specified and a static scheduling is built in the simulation kernel. In [12] the static scheduling is guided by the user via directives to the simulation kernel.…”

Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

“…Then, it proposes to use vci (Virtual Component Interface [1]) communication low level protocol to interface easily various ip. Finally it suggests a certain programming style that enables the possibility of writing very efficient simulation engines (closer to step by step simulation than to event driven simulation [2]). …”

Section: Introductionmentioning

confidence: 99%

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Cycle Accurate Simulation Model Generation for SoC Prototyping

Fraboulet¹,

Risset

Scherrer

2004

Lecture Notes in Computer Science

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We present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new computation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the SocLib cycle accurate simulation environment. This integration also validates an efficient generic interface mechanism for data-flow ips.

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Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

Section: Fsm Representation For Rtl Simulation Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Cycle Accurate Simulation Model Generation for SoC Prototyping

Fraboulet¹,

Risset

Scherrer

2004

Lecture Notes in Computer Science

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“…The second component in COSYS is the high speed simulation environment for hardware/software co-simulation. PISIM (Petrot et al 1997) is a cycle-based simulator that can simulate more than I 00 000 MIPS instructions per second. The hardware components in the system can be described in C or VHDL, as long as they behave as synchronous FSMs.…”

Section: The Co-simulation and Co-synthesis Environmentmentioning

confidence: 99%

User Guided High Level Synthesis

Augé

Bawa

Galle

et al. 1997

VLSI: Integrated Systems on Silicon

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This paper presents a High Level Synthesis (HLS) method for specialized coprocessors in embedded systems. In recent years, the synthesis of hardware systems has moved to a higher level of abstraction, but the existing tools leave very little initiative to the designer. With User Guided High Level Synthesis (UGH), we introduce the notion of Draft Data-Path Scheme (OOPS) which we consider an efficient way for the user to guide the HLS process. It describes the general structure of the datapath, without detailed information like signal-widths or physical implementation of multiplexers. Guided by these structural constraints, UGH intends to deliver a full data-path and a scheduled Finite State Machine that takes into account the detailed timing characteristics of the target physical library.

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User Guided High Level Synthesis

Augé

Pétrot

High-Level Synthesis

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The User Guided Synthesis approach targets the generation of coprocessor under timing and resource constraints. Unlike other approaches that discover the architecture through a specific interpretation of the source code, this approach requires that the user guides the synthesis by specifying a draft of its data-path architecture. By providing this information, the user can get nearly the expected design in one shot instead of obtaining an acceptable design after an iterative process. Of course, providing a data-path draft limits its use to circuit designers. The approach requires three inputs: The first input is the description of the algorithm to be hardwired. It is purely functional, and does not contain any statement or pragma indicating cycle boundaries. The second input is a draft of the data-path on which the algorithm is to be executed. The third one is the target frequency of the generated hardware. The synthesis method is organized in two main tasks. The first task, called Coarse Grain Scheduling, targets the generation of a fully functional data-path. Using the functional input and the draft of the data-path (DDP), that basically is a directed graph whose nodes are functional or memorization operators and whose arcs indicate the authorized data-flow among the nodes, this task generates two outputs : - The first one is a RT level synthesizable description of the final coprocessor datapath, by mapping the instructions of the functional description on the DDP.- The second one is a coarse grain finite state machine in which each operator takes a constant amount of time to execute. It describes the flow of control without knowledge of the exact timing of the operators, but exhibits the parallelism among the instruction flow. The data-path is synthesized, placed and routed with back-end tools. After that, the timings such as propagation, set-up and hold-times, are extracted and the second task, called Fine Grain Scheduling, takes place. It basically performs the retiming of the Coarse Grain finite state machine taking into account the target frequency and the fine timings of the data-path implementation. Compared to the classical High Level Synthesis approaches, the User Guided Synthesis induces new algorithmic problems. For Coarse Grain Scheduling, it consists of finding whether an arithmetic and logic expression of the algorithmic input can be mapped on the given draft data-path or not, and when several mappings are found, to choose the one that maximizes the parallelism and minimizes the added resources. So the Coarse Grain Scheduling can be seen as a classical compiler, the differences being firstly that the target instruction set is not hardwired in the compiler but described fully or partially in the draft data-path, and secondly that a small amount of hardware can be added by the tools to optimize speed. For Fine Grain Scheduling, it consists of reorganizing the finite state machine to ensure that the data-path commands are synchronized with the execution delays of the operators they control. The fine ...

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A simulation environment for core based embedded systems

Cited by 10 publications

References 12 publications

Cycle Accurate Simulation Model Generation for SoC Prototyping

Cycle Accurate Simulation Model Generation for SoC Prototyping

User Guided High Level Synthesis

User Guided High Level Synthesis

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