Cycle Accurate Simulation Model Generation for SoC Prototyping

Fraboulet, Antoine; Risset, Tanguy; Scherrer, Antoine

doi:10.1007/978-3-540-27776-7_47

Cited by 6 publications

(11 citation statements)

References 13 publications

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“…They were originally published in [26]. In the right figure, we added a curve With 20 % Slowdown following the results of the parallelization of the avionics application, a optimization for minimal approximated execution time and minimal number of cores (cut at 16). Times are all evaluated configurations, diamond are optimal configurations representing the Pareto front, b Approximated optimal speedups for different numbers of cores with/without parallelization overheads and with assuming a slowdown of 20 % for each utilized core the Pareto front.…”

Section: Results Of the Model-based Optimizationmentioning

confidence: 99%

“…In our case, the hardware is the , which is an experimental multicore processor developed in the parMERASA project [56]. It is implemented in a cycle-accurate simulator based on SoCLib 13 [16]. The parMERASA platform is built in a way that facilitates WCET analysability, e. g. by ensuring deterministic behaviour and avoiding speculative components (since in the worst case it always has to be assumed that speculation fails).…”

Section: Applying Phase I On the Signal Processing Applicationmentioning

confidence: 99%

“…16 Since the pipeline is unbalanced and there is more parallelization potential in its largest activity a to A, we try to distribute this activity on 8 and 16 cores. The WCET results are also shown in Table 3.…”

Section: Applying Refinement On the Signal Processing Applicationmentioning

confidence: 99%

“…Therefore, every time the largest stage is finished, one result matrix comes out of the pipeline 16. In the sequential version, all activities have to be processed to get one result matrix.…”

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confidence: 99%

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A Parallelization Approach for Hard Real-Time Systems and Its Application on Two Industrial Programs

Frieb

Jahr

Ozaktas

et al. 2016

Int J Parallel Prog

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Applications in industry often have grown and improved over many years. Since their performance demands increase, they also need to benefit from the availability of multi-core processors. However, a reimplementation from scratch and even a restructuring of these industrial applications is very expensive, often due to high certification efforts. Therefore, a strategy for a systematic parallelization of legacy code is needed. We present a parallelization approach for hard real-time systems, which ensures a high reusage of legacy code and preserves timing analysability. To show its applicability, we apply it on the core algorithm of an avionics application as well as on the control program of a large construction machine. We create models of the legacy programs showing the potential of parallelism, optimize them and change the source codes accordingly. The parallelized applications are placed on a predictable multi-core processor with up to 18 cores. For evaluation, we compare the worst case execution times and their speedups. Furthermore, we analyse limitations coming up at the parallelization process.

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Section: Results Of the Model-based Optimizationmentioning

confidence: 99%

Section: Applying Phase I On the Signal Processing Applicationmentioning

confidence: 99%

Section: Applying Refinement On the Signal Processing Applicationmentioning

confidence: 99%

mentioning

confidence: 99%

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A Parallelization Approach for Hard Real-Time Systems and Its Application on Two Industrial Programs

Frieb

Jahr

Ozaktas

et al. 2016

Int J Parallel Prog

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“…This signal acts as a virtual clock and establishes a correspondence between the virtual time ¥ R 6 9 & 6 F given by the schedule and the actual clock of the circuit. The use of virtual clocks ensures that the behavior of the architecture is really the one that is expected after scheduling, and in addition, it allows the architecture to be easily integrated as an IP [13] in a complex design. For reasons related to the size, the power consumption, or the throughput of the resulting architecture, a designer might prefer a multi-dimensional schedule for this program, for instance:…”

Section: Motivating Examplementioning

confidence: 99%

Hardware synthesis for systems of recurrence equations with multidimensional schedule

Guillou

Quinton

Risset

2008

IJES

Self Cite

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Abstract-This paper introduces methods for extending the classical systolic synthesis methodology to multidimensional time. Multi-dimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it requires the use of memories in the architecture. The synthesis of such an architecture requires the definition of an allocation function that maps the calculations on the processors, and memory functions that define where the data are stored during execution. As our approach targets custom VLSI architectures, we constrain the synthesis method to produce parallel architectures that that satisfy the computer owns rule, i.e., each processor computes the data which are stored in its local memory. We explain how to combine the allocation and memory functions in order to meet the computer owns rule, and we present an original mechanism for controlling the operation of the architecture. We detail the different steps needed to generate a HDL description of the architecture, and we illustrate our method on the matrix multiplication algorithm. We describe a structural VHDL program that has been derived and synthesized for a FPGA platform using these design principles. Our results show that the complexity added in each processor by the memories and the control is moderate and justifies in practice the use of such architectures.

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