A simulation framework for domain-specific system-on-chips

Arda, Samet E.; Nk, Anish; Goksoy, A. Alper; Mack, Joshua; Kumbhare, Nirmal; Sartor, Anderson L.; Akoglu, Ali; Mărculescu, Radu; Ogras, Ümit Y.

doi:10.1145/3349567.3351719

Cited by 3 publications

(4 citation statements)

References 9 publications

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“…This section provides an extension to our previous work in [41], using built-in DS3 schedulers and applications in the benchmark suite. The simulations run on an SoC configuration that mimics a typical heterogeneous SoC with a total of 16 general purpose cores and hardware accelerators: 4 big Arm Cortex-A15 cores, 4 LITTLE Arm Cortex-A7, 2 scrambler accelerators, 4 FFT accelerators, and 2 Viterbi decoders.…”

Section: Scheduler Case Studiesmentioning

confidence: 99%

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

Arda

Krishnakumar

Goksoy

et al. 2020

IEEE Trans. Comput.

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Heterogeneous systems-on-chip (SoCs) are highly favorable computing platforms due to their superior performance and energy efficiency potential compared to homogeneous architectures. They can be further tailored to a specific domain of applications by incorporating processing elements (PEs) that accelerate frequently used kernels in these applications. However, this potential is contingent upon optimizing the SoC for the target domain and utilizing its resources effectively at runtime. To this end, system-level design -including scheduling, power-thermal management algorithms and design space exploration studies -plays a crucial role. This paper presents a system-level domain-specific SoC simulation (DS3) framework to address this need. DS3 enables both design space exploration and dynamic resource management for power-performance optimization of domain applications. We showcase DS3 using six real-world applications from wireless communications and radar processing domain. DS3, as well as the reference applications, is shared as open-source software to stimulate research in this area.

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Section: Scheduler Case Studiesmentioning

confidence: 99%

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

Arda

Krishnakumar

Goksoy

et al. 2020

IEEE Trans. Comput.

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“…The WiFi transmitter and receiver applications process 64 bits of data in one frame and are segmented into the kernels shown in Figure 7. It is composed of various compute-intensive blocks, such as FFT, modulation, demodulation, Viterbi decoder, and scrambler [13]. Range detection and Pulse Doppler applications are used in Radar to determine the distance and velocity, respectively, of the target object from the reference signal source.…”

Section: B Hardware Platforms and Applicationsmentioning

confidence: 99%

“…Our framework is successfully able to expose the limitations of underlying design decisions related to the SoC configuration and scheduling policies for a given set of applications. Traditionally, researchers use discrete event-based simulation tools, such as DS3 [13] and SimGrid [14], to develop and evaluate new scheduling algorithms. These simulators rely on statistical profiling information to realize the performance of general-purpose cores and hardware accelerators.…”

Section: Case Study 2: Performance Modementioning

confidence: 99%

“…In modern SoC design, pre-silicon verification is the most resource-intensive phase involving functional correctness and constraint checks on the SoC [19]. Considering a three layered approach to SoC design with hardware, resource management and application layers, both, discrete-event [13], [14] and cycle-accurate [15]- [17] based simulation approaches address the challenges involving each layer in isolation. As shown in Section III-D, our user-space emulation framework provides an environment where these three layers are considered in tandem.…”

Section: Literature Surveymentioning

confidence: 99%

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User-Space Emulation Framework for Domain-Specific SoC Design

Mack¹,

Kumbhare²,

NK³

et al. 2020

Preprint

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In this work, we propose a portable, Linux-based emulation framework to provide an ecosystem for hardwaresoftware co-design of Domain-specific SoCs (DSSoCs) and enable their rapid evaluation during the pre-silicon design phase. This framework holistically targets three key challenges of DSSoC design: accelerator integration, resource management, and application development. We address these challenges via a flexible and lightweight user-space runtime environment that enables easy integration of new accelerators, scheduling heuristics, and user applications, and we illustrate the utility of each through various case studies. With signal processing (WiFi and RADAR) as the target domain, we use our framework to evaluate the performance of various dynamic workloads on hypothetical DSSoC hardware configurations composed of mixtures of CPU cores and FFT accelerators using a Zynq UltraScale+ TM MPSoC. We show the portability of this framework by conducting a similar study on an Odroid platform composed of big.LITTLE ARM clusters. Finally, we introduce a prototype compilation toolchain that enables automatic mapping of unlabeled C code to DSSoC platforms. Taken together, this environment offers a unique ecosystem to rapidly perform functional verification and obtain performance and utilization estimates that help accelerate convergence towards a final DSSoC design.

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User-Space Emulation Framework for Domain-Specific SoC Design

Mack

Kumbhare

et al. 2020

2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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A simulation framework for domain-specific system-on-chips

Cited by 3 publications

References 9 publications

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

User-Space Emulation Framework for Domain-Specific SoC Design

User-Space Emulation Framework for Domain-Specific SoC Design

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