DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

Arda, Samet E.; Krishnakumar, Anish; Goksoy, A. Alper; Kumbhare, Nirmal; Mack, Joshua; Sartor, Anderson L.; Akoglu, Ali; Mărculescu, Radu; Ogras, Ümit Y.

doi:10.1109/tc.2020.2986963

Cited by 32 publications

(14 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…DS3 [14] (system-level domain-specific SoC simulation) is a system-level domain-specific SoC simulation platform. It leverages Dynamic Power and Thermal Management (DTPM) methodologies to provide users with a tool for resource optimization including the SoC design space.…”

Section: Ds3mentioning

confidence: 99%

See 1 more Smart Citation

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Alali

Elmaaradi

Khaldoun

et al. 2021

IJEEI

View full text Add to dashboard Cite

Systems-on-a-chip integrates specialized modules to provide well-defined functionality. To guarantee its efficiency, designers are careful to choose highlevel electronic components. In particular, FPGAs (field-programmable gate array) have demonstrated their ability to meet the requirements of emerging technology. However, traditional design methods cannot keep up with the speed and efficiency imposed by the embedded systems industry, so several frameworks have been developed to simplify the design process of an electronic system, from its modeling to its physical implementation. This paper illustrates some of them and presents a comparative study between them. Indeed, we have selected design methods of SoC (ESP4ML and HLS4ML, OpenESP, LiteX, RubyRTL, PyMTL, SysPy, PyRTL, DSSoC) and NoC networks on OCN chip (PyOCN) and in general on FPGA (PRGA, OpenFPGA, AnyHLS, PYNQ, and PyLog). The objective of this article is to analyze each tool at several levels and to discuss the benefit of each in the scientific community. We will analyze several aspects constituting the architecture and the structure of the platforms to make a comparative study of the hardware and software design flows of digital systems.

show abstract

Section: Ds3mentioning

confidence: 99%

“…✓ Scheduling and DTPM Algorithms: DS3 [14] includes Dynamic Power and Thermal Management policies and scheduling algorithms, which will allow designers to model and implement new algorithmic procedures. It is thanks to the Scheduler class and the constructor functions that the user creates his algorithm.…”

mentioning

confidence: 99%

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Alali

Elmaaradi

Khaldoun

et al. 2021

IJEEI

View full text Add to dashboard Cite

show abstract

“…We conduct our evaluations in the open-source DS3 environment [14] that allows the designer to simulate the behavior of a heterogeneous platform under a variety of realistic SoC workload scenarios, resource management strategies, and hardware configurations. DS3 enables simulations of benchmark applications, modeled as DAGs, considering a target heterogeneous SoC platform under different scheduling algorithms.…”

Section: Simulation Frameworkmentioning

confidence: 99%

“…Table shows execution time for each task on each PE. Gantt chart shows output schedule generated via the DS3 simulation environment [14]. In this scenario, all link speeds between distinct PEs are assumed to be 1 in accordance with [5], and the edge weights in the DAG represent the total volume of data that must be transferred over those links.…”

Section: Introductionmentioning

confidence: 99%

Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices

Mack¹,

Arda²,

Ogras³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

Performance-, power-, and energy-aware scheduling techniques play an essential role in optimally utilizing processing elements (PEs) of heterogeneous systems. List schedulers, a class of low-complexity static schedulers, have commonly been used in static execution scenarios. However, list schedulers are not suitable for runtime decision making, particularly when multiple concurrent applications are interleaved dynamically. For such cases, the static task execution times and expectation of idle PEs assumed by list schedulers lead to inefficient system utilization and poor performance. To address this problem, we present techniques for optimizing execution of list scheduling algorithms in dynamic runtime scenarios via a family of algorithms inspired by the well-known heterogeneous earliest finish time (HEFT) list scheduler. Through dynamically arriving, realistic workload scenarios that are simulated in an open-source discrete event heterogeneous SoC simulator, we exhaustively evaluate each of the proposed algorithms across two SoCs modeled after the Xilinx Zynq Ultrascale+ ZCU102 and O-Droid XU3 development boards. Altogether, depending on the chosen variant in this family of algorithms, we are able to achieve an up to 39% execution time improvement, up to 7.24x algorithmic speedup, or up to 30% energy consumption improvement compared to the baseline HEFT implementation.

show abstract

“…A discrete-event Domain-Specific System-on-Chip Simulation (DS3) is a real-time system-level emulator that is built for scheduling tasks to general-purpose and special-purpose processors, especially optimizing the processors to a particular domain [10]. It is known as domain-specific system-on-chips (DSSoCs), a class of heterogeneous architectures.…”

Section: Ds3 Simulationmentioning

confidence: 99%

DeepSoCS: A Neural Scheduler for Heterogeneous System-on-Chip (SoC) Resource Scheduling

Sung

Kim

et al. 2020

Electronics

View full text Add to dashboard Cite

In this paper, we present a novel scheduling solution for a class of System-on-Chip (SoC) systems where heterogeneous chip resources (DSP, FPGA, GPU, etc.) must be efficiently scheduled for continuously arriving hierarchical jobs with their tasks represented by a directed acyclic graph.Traditionally, heuristic algorithms have been widely used for many resource scheduling domains, and Heterogeneous Earliest Finish Time (HEFT) has been a dominating state-of-the-art technique across a broad range of heterogeneous resource scheduling domains over many years. Despite their long-standing popularity, HEFT-like algorithms are known to be vulnerable to a small amount of noise added to the environment. Our Deep Reinforcement Learning (DRL)-based SoC Scheduler (DeepSoCS), capable of learning the "best" task ordering under dynamic environment changes, overcomes the brittleness of rule-based schedulers such as HEFT with significantly higher performance across different types of jobs. We describe a DeepSoCS design process using a real-time heterogeneous SoC scheduling emulator, discuss major challenges, and present two novel neural network design features that lead to outperforming HEFT: (i) hierarchical job-and task-graph embedding; and (ii) efficient use of real-time task information in the state space. Furthermore, we introduce effective techniques to address two fundamental challenges present in our environment: delayed consequences and joint actions. Through an extensive simulation study, we show that our DeepSoCS exhibits the significantly higher performance of job execution time than that of HEFT with a higher level of robustness under realistic noise conditions. We conclude with a discussion of the potential improvements for our DeepSoCS neural scheduler.

show abstract

DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework

Cited by 32 publications

References 36 publications

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

The review of heterogeneous design frameworks/Platforms for digital systems embedded in FPGAs and SoCs

Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices

DeepSoCS: A Neural Scheduler for Heterogeneous System-on-Chip (SoC) Resource Scheduling

Contact Info

Product

Resources

About