A Simulation Platform for the Study of Soft Errors on Signal Processing Circuits through Software Fault Injection

Ruano, O.; Maestro, Juan Antonio; Reyes, Pablo; Reviriego, Pedro

doi:10.1109/isie.2007.4375147

Cited by 16 publications

(6 citation statements)

References 8 publications

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“…Next, the checking process is carried out on (1) through an iterative engine (2) based on an optimization algorithm [4], which drives a simulation fault injection routine (3). This methodology measures the Error Rate of the given fault tolerant system in (1.1) through an SEU simulation tool called SST [5] that performs a fault campaign according to (4) (in term of the number of SEUs). Then, the final circuit with selective TMR is tested with a campaign of injected errors.…”

Section: Proposed Methodologymentioning

confidence: 99%

Validation and optimization of TMR protections for circuits in radiation environments

Ruano

Maestro

Reviriego

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Section: Proposed Methodologymentioning

confidence: 99%

Validation and optimization of TMR protections for circuits in radiation environments

Ruano

Maestro

Reviriego

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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“…As an example, some tools based on these techniques are: SST [ 33 , 34 ], MEFISTO [ 35 ] and VERIFY [ 36 ]. In all these cases, the failure model described is for an ASIC.…”

Section: Background Conceptsmentioning

confidence: 99%

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

Ruano

García-Herrero

Aranda

et al. 2021

Sensors

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Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

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“…In recent years, both simulation and emulation-based fault injection platforms have been documented in the literature. Simulation environments or tools such as XCEPTION [10], SST [11], MEFISTO [12], or VERIFY [13] are some examples. They all try to reproduce the behavior of a hardware circuit under specific undesirable malfunctions from its highlevel description by using a commercial or ad-hoc simulator.…”

Section: Existing Fault Emulation Platformsmentioning

confidence: 99%

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

et al. 2021

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There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

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A Simulation Platform for the Study of Soft Errors on Signal Processing Circuits through Software Fault Injection

Cited by 16 publications

References 8 publications

Validation and optimization of TMR protections for circuits in radiation environments

Validation and optimization of TMR protections for circuits in radiation environments

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

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