a b s t r a c tThe new IEEE 802.3az Energy Efficient Ethernet (EEE) standard will improve significantly the energy efficiency of 10 Gbps copper transceivers by the introduction of a sleep mode for idle transmission times. The next step towards energy saving seems to be the application of similar concepts to Optical Ethernet, both for short and long range links. To this aim, this paper starts by proposing an analytical model to estimate the energy consumption of a link that uses a sleep-mode power saving mechanism. This model can be useful to answer a number of questions that need to be carefully studied. Otherwise, the complexity of optical components could be increased for the sake of an energy saving that could turn out negligible. In the rest of the paper we analyze three key questions to try to shed some light on this design decision: (a) is the new copper EEE actually outperforming the current regular optical Ethernet in terms of energy saving in such a way that optical PHYs (transceivers) actually need a green upgrade to remain more energy efficient than their copper counterparts? (b) How much energy saving could be actually achieved by EE optical Ethernet? (c) What is the transition time required to achieve a substantial energy saving at medium traffic loads on EE 10 Gb/s optical Ethernet links? The answer to the latter question sets a concrete goal for short-term research in fast on-off laser technology.

Radiation particles can impact registers or memories creating soft errors. These errors can modify more than one bit causing a Multiple Cell Upset (MCU) which consists of errors in registers or memory cells physically close. These MCUs can affect a single word, producing adjacent bit errors. Hamming codes are commonly used to protect memories or registers from soft errors. However, when multiple errors occur a Hamming code may not detect them. In this letter, Single Error Correction Double Adjacent Error Detection (SEC-DAED) Hamming codes are presented for 16, 32 and 64-bit words. Additionally, Single Error Correction Double Error Detection Triple Adjacent Error Detection (SEC-DED-TAED) codes based on Extended Hamming are presented as well. The enhanced detection is achieved by performing a selective shortening and reordering of the Hamming matrix so adjacent errors result in a syndrome that does not match that of any single error. These codes will help in the detection of MCUs in SRAM memory designs.

Abstract-Static

International audienceThis article presented a survey of dependability issues faced by multi-core architectures at nanoscale technology nodes. Existing solutions against these challenges were also discussed, describing their scope of application, from technology level methodologies, to design approaches to the metrics required to evaluate the overall dependability of a system. In the future, the constant reduction of the feature size of the devices will exacerbate the issues related to aging and soft errors. This will create further challenges and at design level, an integrated design approach that will cope with the occurrence of faults at any time of their occurrence i.e., at manufacturing (thus increasing yield) and in the field (thus increasing reliability) will become more and more important to obtain economically viable and dependable systems. Dependability assessment will also need an integrated approach for cross-layer, pre- and post-silicon techniques for “just right”dependability assessment in order to avoid “overdesign”for dependability using classic guard-banding methodologies

Abstract-Error correction codes (ECCs) have been used for decades to protect memories from soft errors. Single error correction (SEC) codes that can correct 1-bit error per word are a common option for memory protection. In some cases, SEC codes are extended to also provide double error detection and are known as SEC-DED codes. As technology scales, soft errors on registers also became a concern and, therefore, SEC codes are used to protect registers. The use of an ECC impacts the circuit design in terms of both delay and area. Traditional SEC or SEC-DED codes developed for memories have focused on minimizing the number of redundant bits added by the code. This is important in a memory as those bits are added to each word in the memory. However, for registers used in circuits, minimizing the delay or area introduced by the ECC can be more important. In this paper, a method to construct low delay SEC or SEC-DED codes that correct errors only on the data bits is proposed. The method is evaluated for several data block sizes, showing that the new codes offer significant delay reductions when compared with traditional SEC or SEC-DED codes. The results for the area of the encoder and decoder also show substantial savings compared to existing codes.Index Terms-Double error detection, error correction codes (ECCs), single error correction (SEC), soft errors.