A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only

Reviriego, Pedro; Pontarelli, Salvatore; Maestro, Juan Antonio; Ottavi, Marco

doi:10.1109/tcad.2012.2226585

Cited by 44 publications

(23 citation statements)

References 11 publications

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“…Finally, Low Delay (LD) codes proposed in [27] and [28] can be applied to CPU registers protection. They share objectives with our proposal.…”

Section: B Faster Error Control Codesmentioning

confidence: 99%

“…Low Delay (LD) SEC and SEC-DED codes [27] reduce the time required to correct 1-bit errors when only the correction of data bits is needed. These codes take advantage of the minor interest of correcting parity bits in registers, as the information stored is not rewritten in the same register once it has been read, and the input data come from other processor elements.…”

Section: Low Delay Codesmentioning

confidence: 99%

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Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

et al. 2019

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Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption. INDEX TERMS Adjacent error correction, double error detection, error control codes, fast codes, reliability.

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“…Finally, Low Delay (LD) codes proposed in [27] and [28] can be applied to CPU registers protection. They share objectives with our proposal.…”

Section: B Faster Error Control Codesmentioning

confidence: 99%

Section: Low Delay Codesmentioning

confidence: 99%

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

et al. 2019

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“…Recently, a method to optimize the decoding of SEC and SEC-DED codes with constant weight has been presented [13]. This scheme is based on the observation that when all the data columns in the H matrix have the same weight, errors can be located by checking only that the ones in the syndrome match those in the data column.…”

Section: Proposed Sec-daec Codesmentioning

confidence: 99%

“…A method to reduce the decoding complexity for some SEC and SEC-DED codes has been recently proposed in [13]. The scheme focuses on codes with constant weight on the data columns of the parity check matrix.…”

Section: Introductionmentioning

confidence: 99%

A Method to Design SEC-DED-DAEC Codes With Optimized Decoding

Reviriego

Martinez

Pontarelli

et al. 2014

IEEE Trans. Device Mater. Relib.

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Single error correction-double error detectiondouble adjacent error correction (SEC-DED-DAEC) codes have been proposed to protect SRAM devices from multiple cell upsets (MCUs). The correction of double adjacent errors ensures that the most common types of MCUs are corrected. At the same time, SEC-DED-DAEC codes require the same number of parity check bits as traditional SEC-DED codes. The main overhead associated with SEC-DED-DAEC codes is the increase in decoding complexity that can impact access time and circuit power and area. In this paper, a method to design SEC-DED-DAEC codes with optimized decoding is presented and evaluated. The proposed scheme starts by setting some constraints on the parity check matrix of the codes. Those constraints are then used to simplify the decoding. The proposed scheme has been implemented and evaluated for different word-lengths. The results show that, for data words of 32 bits, the scheme can be implemented with the same number of parity check bits as SEC-DED codes. For 16 and 64 bits words, an additional parity check bit is required, making the scheme less attractive. With the proposed method, the decoders can be optimized for area or speed. Both implementations are evaluated and compared with existing SEC-DED-DAEC decoders. The results show that the proposed decoders reduce significantly the circuit area, power, and delay.

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“…Fault tolerant approaches instead target at tolerating the occurrence of the bit flips at system level by adding different redundancy approaches such as coding (information redundancy) TMR/DMR (hardware redundancy) repeated operations (time redundancy) [7]. Depending on the size and the use of the memory to be protected (register files, cache memories, main memories, storage memories), different ECCs have been used [8], [9], [10], [11]. However, these techniques are not suitable for the protection of single memory elements such as latches or flip-flops.…”

Section: Introductionmentioning

confidence: 99%

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

Campitelli

Ottavi

Pontarelli

et al. 2013

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.

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A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only

Cited by 44 publications

References 11 publications

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection

A Method to Design SEC-DED-DAEC Codes With Optimized Decoding

F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

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