2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) 2013
DOI: 10.1109/dft.2013.6653591
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F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

Abstract: This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed … Show more

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Cited by 15 publications
(9 citation statements)
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“…Note that, in Fig. 1 [13][14][15][16][17][18][19]23], and so on. Similarly, to achieve high reliability, many hardened FFs protected against DNUs have been proposed.…”
Section: Introductionmentioning
confidence: 99%
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“…Note that, in Fig. 1 [13][14][15][16][17][18][19]23], and so on. Similarly, to achieve high reliability, many hardened FFs protected against DNUs have been proposed.…”
Section: Introductionmentioning
confidence: 99%
“…To mitigate SNUs and DNUs, radiation hardening by design (RHBD) is a widely employed approach. Using RHBD, many novel storage elements, such as latches [5][6][7][8], static random access memories (SRAMs) [9][10][11][12], and flip-flops (FFs) [13][14][15][16][17][18][19]23] have been proposed. Among them, dual-interlocked storage-cells (DICEs) are widely used [20].…”
Section: Introductionmentioning
confidence: 99%
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“…The DICE has good trade-off between soft error tolerant capability and performance and then many researchers have studied its extension. For example, F-DICE [6], Delta DICE [7] and DONUT latches [8], [9] have multiple-nodeupset (MNU) tolerant capability while the original DICE is capable of tolerating only SNUs. The DF-DICE [10] and the FF of [11] is capable of tolerating single-event-transients (SETs) as well as SEUs by using delay elements.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, the particle may directly strike an OFF-state transistor in a storage element, causing a single-node upset (SNU). Moreover, with the aggressive CMOS technology scaling, circuit integration is becoming much higher and node To mitigate SNUs or even DNUs, using radiation hardening by design (RHBD) techniques, many novel designs of latches [5][6][7] and flip-flops [8][9][10] are proposed, while the other designs mainly consider hardening for static random access memory (SRAM) cells [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. This paper mainly considers hardening for SRAMs.…”
Section: Introductionmentioning
confidence: 99%