Dependable Multicore Architectures at Nanoscale: The View From Europe

Abstract

International audienceThis article presented a survey of dependability issues faced by multi-core architectures at nanoscale technology nodes. Existing solutions against these challenges were also discussed, describing their scope of application, from technology level methodologies, to design approaches to the metrics required to evaluate the overall dependability of a system. In the future, the constant reduction of the feature size of the devices will exacerbate the issues related to aging and soft errors. This will create further challenges and at design level, an integrated design approach that will cope with the occurrence of faults at any time of their occurrence i.e., at manufacturing (thus increasing yield) and in the field (thus increasing reliability) will become more and more important to obtain economically viable and dependable systems. Dependability assessment will also need an integrated approach for cross-layer, pre- and post-silicon techniques for “just right”dependability assessment in order to avoid “overdesign”for dependability using classic guard-banding methodologies

Multi-core Devices for Safety-critical Systems

“…In these domains, the embedded systems often play a crucial role in guaranteeing the overall safety of the system. These systems are referred to as safety-critical systems as their failure can derive into catastrophic consequences such as the loss of lives or severe environmental damage [1] (e.g., automotive cruise control [2], railway signalling [3], wind turbine integrity protection [4], pacemaker [5]). With the aim of reducing the risk of causing such fatalities, safety-critical systems must follow strict certification processes according to domain specific safety standards.…”

“…The usage of mono-core devices with higher frequency is considered not competitive in several domains due to increased sensibility to Electromagnetic Interference (EMI) [16], low reliability of thermal dissipation fans [8,4] and cooling systems volume and weight [17]. On the other hand, Commercial Off-The-Shelf (COTS) multi-core devices are becoming dominant in silicon manufacturer roadmaps [18,19,20,12,21,22,10] and provide a cross-domain potential solution, e.g., automotive [23,15,2], avionics [24,10], railway [3,25], industrial control [6,26], medical applications [5].…”

“…This publication is a survey on multi-core devices for safety-critical systems. The bulk of the research in multi-core devices for dependable systems focuses on specific challenges such as device and component architectures, reliability, time predictability and safety certification strategies [7,5]. This survey however, aims to provide a categorization and end-to-end view of safety implications on multi-core devices, starting from nanoscale level and up to device level, by bringing together and summarizing the most relevant research contributions that support the compliance with fundamental safety technical requirements.…”

Reliability-Aware Task Allocation Latency Optimization in Edge Computing

“…By offloading tasks from the cloud to the edge [1], [2], we reduce network traffic and enable real-time data processing/analytics. However, as CMOS technology keeps shrinking and devices are operating with near-threshold voltages, the reliability of embedded hardware systems is compromised due to various dependability threats caused by aging-related failures, as well as, environmental conditions such as soft-errors [3], [4]. Therefore, as we move away from the cloud and towards the edge, the devices become error-prone and the reliability of the system begins to degrade [5].…”

RIIF-2: Toward the next generation reliability information interchange format

“…However, technology scaling is evolving so quickly that this approach is impacting the performance, area, and power benefits of new technologies to a level that makes reliability oriented overdesign economically not sustainable [3]. To overcome this limit, cross-layer approaches in which reliability levels of complex systems are sustained by techniques that operate at all levels of the system stack (i.e., technology, hardware architecture and software) have been proposed [4][5] [6][7] [8]. The research community often focuses on efficient implementations of cross-layer approaches for a specific sample design.…”