A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

Abstract

In this paper we investigate the influence of incorporating HfO2 as a dielectric at the drain side and silicon stack at the source side on the electrical performance of a double gate tunnel FET (DG-TFET). For this, we compare a conventional TFET structure with four other structures in which their gate dielectric material is either homogenous or heterogeneous while the insulator in the drain side is either SiO2 or HfO2. Moreover, a structure with silicon source stack has been proposed and the device figures of merit are compared with other counterparts. Our simulation results reveal the fact that the presence of HfO2 insulator in the drain side reduces the ambipolar conduction while heterogeneous gate dielectric enhances the drive current and transconductance. However, HfO2 slightly deteriorates source-gate and drain-gate capacitances compared to conventional TFET. Furthermore, incorporation of silicon source stack along with heterogeneous gate dielectric and HfO2 insulator in the drain side lead to higher ION/IOFF ratio, lower subthreshold slope (S), and lower ambipolar conduction in a 50 nm channel length TFET under study.

WITHDRAWN: Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

“…In this paper, prior to this work, several literatures were surveyed based on structural and material engineering [4][5][6][7][8][9][10][11][12][13][14]. The effect of homogeneous and heterogeneous material in tunneling junctions [15], effect of pocket intrinsic doping on single as well as multi gate tunneling FETs [16][17], effect of device performance based on various high-k materials [18], stress-strain effects in source-channel (n-channel) and drain-channel (pchannel) TJDs [19], usage of carbon nano-tubes (CNT) in tunneling FETs [20], nano-wire tunneling FETs [21], capacitive effects in modified TJD structures [22], various symmetric and asymmetric tunneling device structures has been studied to meet the earlier mentioned scaling issues and device performance factors.…”

A Study on the Performance of Gate-All-Around Heterojunction Tunnel Field-Effect Transistors Based on Polarization Effect

“…The gate dielectric plays a pivotal role in the TFET devices as it determines the extent of gate control over the channel by coupling with the gate dielectric capacitance . The studies have suggested that utilizing high-κ gate dielectrics, in contrast to silicon dioxide, can enhance the gate’s control over the channel surface and improve tunnel junction characteristics in TFETs. , Moreover, as the device dimensions decrease, reducing the thickness of the gate dielectric layer becomes imperative to effectively address the short-channel effects. However, excessively thin gate dielectric layers may induce quantum tunneling effects from the channel to the gate electrode, resulting in gate leakage current.…”

Performance Investigation of Source Extension Approach on III–V Vertical Tunnel FET

“…Source Extension-Based TFETs extend the source region beyond the gate edge to alter the electric field distribution and decrease the tunneling barrier width near the source side [11]. This boosts the pace of tunneling and promotes device function [12]. Tunnel FETs based on source extension are recognized for their straightforward fabrication and ability to enhance the ON-state current and subthreshold swing [13].…”