A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

Czutro, Alexander; Houarche, Nicolas; Engelke, Piet; Polian, Ilia; Comte, Mariane; Renovell, Michel; Becker, Bernd

doi:10.1109/ets.2008.19

Cited by 44 publications

(46 citation statements)

References 14 publications

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“…An example industrial application of defectbased test is reported in [19]. Of specific importance in the context of process variations are defect-based approaches to modeling delay defects, including [8].…”

Section: B Defect-based Testmentioning

confidence: 99%

“…It may be worth considering generating additional tests targeting these faults explicitly, and apply or skip these tests depending on information previously collected. To perform variation-aware test generation, state-of-the-art multiconstrained SAT-based ATPG tools [8] can be employed in a manner indicated in Fig. 2.…”

Section: Emerging Concept: Variation-aware Adaptive Testmentioning

confidence: 99%

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Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Section: B Defect-based Testmentioning

confidence: 99%

Section: Emerging Concept: Variation-aware Adaptive Testmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

Self Cite

View full text Add to dashboard Cite

show abstract

“…The waveform representation and evaluation algorithm presented here is tuned towards 2-valued simulations for maximum efficiency. However, the principle evaluation approach is also applicable to multivalued simulations and waveform representations like in [29].…”

Section: Gpgpu Time Simulation Corementioning

confidence: 99%

“…For each signal and input assignment, the complete history of transitions is stored in a data structure called waveform [27][28][29]. Details on the encoding of a waveform will be given in section IV.…”

Section: B Waveset Capacities and Calibrationmentioning

confidence: 99%

Scan Test Power Simulation on GPGPUs

Holst

Schneider

Wunderlich

2012

2012 IEEE 21st Asian Test Symposium

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The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands.We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.

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“…In previous work, the resistances of opens (RO) have been experimentally characterized for an aluminum process and it was reported that for resistive open faults, RO can vary in the range of a Ohms to Megohms [2]. The distribution of resistance values can be used statistically to compute the fault coverage [23]. According to the resistance of the partial-open fault (RO) and the relative length of the sensitized faulty path to the longest path, a ROF can cause extra delays over several orders of magnitude.…”

Section: Introductionmentioning

confidence: 99%

Multivoltage Aware Resistive Open Fault Model

Mohammadat

Ali

Hussin

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs and their behavior exhibits major dependencies on the supply voltage and test patterns. The widespread utilization of multiple supply voltages in contemporary VLSI designs poses a critical concern as to whether conventional models for resistive opens would still be effective. This is because conventional models do not explicitly model the VDD effect on fault behavior and detectability. Based on experimental analysis of ROFs in multi-VDD environment, we propose a voltage-aware model which divides the full range of open resistances (RO) into continuous behavioral intervals and three detectability ranges. The division of the behavior into intervals is based on monitoring the behavior change versus voltage across the resistance continuum, whereas the detectability ranges are based on finding minimum resistance for small and gross delay faults. It is highlighted that the detectable open resistance range is having a decreased trend with new technologies. Additionally it is shown that the observability of the unique increasing delay behavior with VDD for resistive open is reduced in new technologies. This poses reliability concerns and motivates the use of small delay testing for new technologies.

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A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

Cited by 44 publications

References 14 publications

Towards Variation-Aware Test Methods

Towards Variation-Aware Test Methods

Scan Test Power Simulation on GPGPUs

Multivoltage Aware Resistive Open Fault Model

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