A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Togawa, Nozomu; Sato, Masao; Ohtsuki, Tomi

doi:10.1109/aspdac.1997.600338

“…In order to achieve better runtimes, weighted-edge partitioning is the choice for the placement methodology proposed by Hutton [17]. A network flow based technique is used to solve the hierarchical bi-partitioning for the placement and global routing approach by Togawa [18]. There have been other previous efforts trying to develop faster placement and routing algorithms [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Fast timing-driven partitioning-based placement for island style FPGAs

Maidee

¹

,

Ababei

²

,

Bazargan

³

2003

Proceedings of the 40th Annual Design Automation Conference

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In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR [6]. As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.

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“…In order to achieve better runtimes, weighted-edge partitioning is the choice for the placement methodology proposed by Hutton [17]. A network flow based technique is used to solve the hierarchical bi-partitioning for the placement and global routing approach by Togawa [18]. There have been other previous efforts trying to develop faster placement and routing algorithms [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Fast timing-driven partitioning-based placement for island style FPGAs

Maidee¹,

Ababei²,

Bazargan³

2003

Proceedings of the 40th Conference on Design Automation - DAC '03

1

0

View full text Add to dashboard Cite

In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR [6]. As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.

show abstract

“…In order to achieve better runtimes, weighted-edge partitioning is the choice for the placement methodology proposed by Hutton [17]. A network flow based technique is used to solve the hierarchical bi-partitioning for the placement and global routing approach by Togawa [18]. There have been other previous efforts trying to develop faster placement and routing algorithms [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Fast timing-driven partitioning-based placement for island style FPGAs

Maidee¹,

Ababei²,

Bazargan³

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

View full text Add to dashboard Cite

In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR [6]. As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.

show abstract

A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Cited by 8 publications

References 10 publications

Fast timing-driven partitioning-based placement for island style FPGAs

Fast timing-driven partitioning-based placement for island style FPGAs

Fast timing-driven partitioning-based placement for island style FPGAs

Fast timing-driven partitioning-based placement for island style FPGAs

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