Fast timing-driven partitioning-based placement for island style FPGAs

Maidee, P.; Ababei, C.; Bazargan, K.

doi:10.1109/dac.2003.1219089

Cited by 14 publications

(8 citation statements)

References 18 publications

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“…Recently, researchers [13] have attempted to achieve better initial placements by coupling annealing with other deterministic placement strategies in hope of reducing the overall annealing time. For example, in [14], recursive min-cut partitioning, a faster placement heuristic, is employed to quickly produce better initial placements, thereby requiring the annealer to run only in a lower temperature regime. In [15], an adaptive strategy was proposed to dynamically alter the annealing schedule to better suit the dynamics of the evoluting system states.…”

Section: B Prior Workmentioning

confidence: 99%

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

Lin

Wawrzynek

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper develops a dynamically adaptive stochastic tunneling (DAST) algorithm to avoid the "freezing" problem commonly found when using simulated annealing for circuit placement on field-programmable gate arrays (FPGAs). The main objective is to reduce the placement runtime and improve the quality of final placement. We achieve this by allowing the DAST placer to tunnel energetically inaccessible regions of the potential solution space, adjusting the stochastic tunneling schedule adaptively by performing detrended fluctuation analysis, and selecting move types dynamically by a multi-modal scheme based on Gibbs sampling. A prototype annealing-based placer, called DAST, was developed as part of this paper. It targets the same computer-aided design flow as the standard versatile placement and routing (VPR) but replaces its original annealer with the DAST algorithm. Our experimental results using the benchmark suite and FPGA architecture file which comes with the Toronto VPR5 software package have shown a 18.3% reduction in runtime and a 7.2% improvement in critical-path delay over that of conventional VPR.

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Section: B Prior Workmentioning

confidence: 99%

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

Lin

Wawrzynek

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Prior efforts to reduce FPGA CAD run-times have focused on algorithmic changes [1], [2], [3], [4] or parallelization [5], [6], [7]. In this work, we reduce router run-time via a combined CAD and architecture approach.…”

Section: Introductionmentioning

confidence: 99%

Reducing FPGA Router Run-Time through Algorithm and Architecture

Gort

Anderson

2011

2011 21st International Conference on Field Programmable Logic and Applications

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We propose a new FPGA routing approach that, when combined with a low-cost architecture change, results in a 34% reduction in router run-time, at the cost of a 3% area overhead, with no increase in critical path delay. Our approach begins with traditional PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. Our approach points to a new research direction: reducing FPGA CAD run-time by exploring FPGA architectures and algorithms together.

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“…Partition based placement The partition based placement problem is to map a given circuit which is represented as a hypergraph to some specific location in the physical FPGA region [74]. The iterative placement process starts by partitioning the given hypergraph into two sub-graphs (bi-partitioning) P1 and P2.…”

Section: Placementmentioning

confidence: 99%

Mapping large-scale systems on to high density FPGAs

Herath¹

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First and foremost, I would like to express my heartfelt gratitude to my supervisor and mentor, Prof. Thambipillai Srikanthan, for his valuable guidance, motivation, and support for a successful and uninterrupted Ph.D. journey. Without his dedication in my research project, this Ph.D. would never be a reality. It was a complete privilege to have not only his expertise in the research domain, but also his valuable pieces of advice given as a beautiful human spirit. My warmest gratitude also goes to Dr. Alok Prakash. His enormous support and dedication throughout this research is invaluable. Brainstorming and in-depth technical discussions along with his thorough revision of research writings helped me to produce back to back publications. His assistance to me was always one step ahead of my expectations, and this gratitude will never be enough. I would also like to thank Dr. Lam Siew Kei for strengthening the research topic in the early stages. It is also impossible to forget the support given by Dr. Guiyuan in my research. My sincere appreciation also goes to Dr. Ravi Kumar Satzoda for nourishing my interests in FPGAs towards a Ph.D. I would thankfully like to remind the administrative support of Mr. Jeremiah Chua and Ms. Poh Ling. Mr. Jeremiah's swift responses in technical difficulties I encountered were always helpful. Ms. Poh Ling has always been a strength to me in policies and formalities, especially during candidature extension process when I did not see any hope. I would also like to pay my warmest appreciation for all the beautiful people in NTU canteens who always made me smile with an extra bit of food and care. I was very fortunate to have my friend, Mr. Aung Lwin Phyo beside me during the time got tough in all aspects. His warmest support assisted me in focusing on my research without any worry. His financial support during the confirmation examination is one of the best things I have ever got from a friend. My colleagues, Deshya, and Thilina, has always given their touching support to me throughout my research. Lunch breaks, coffee times with them, and xiv of course, their home-cooked treats has helped me to leave heavy minds behind. I always knew that I could count on them. My colleagues Vijeta and Supriya were sisters to me, who always approached me with the most exceptional help. My confirmation examination could not be a success without them. Max Wang's support during the last mile in this Ph.D. has comforted me to stay on track when nothing seemed to be in my favor. Thank you, all. My family has always been the greatest strength to me. Though my father is not around with me today, he has ensured I grow up this far without any hassle. My mother has given the love of both parents since my father's passing, that I found the worth in this tough journey. My two sisters, my brother, and my brother-in-law, were always my best friends that anyone can envy. Their support in this research was always silent and often disguised as a box of rice, a dessert, a car ride, or even as hidden beautiful gifts. But...

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Fast timing-driven partitioning-based placement for island style FPGAs

Cited by 14 publications

References 18 publications

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling

Reducing FPGA Router Run-Time through Algorithm and Architecture

Mapping large-scale systems on to high density FPGAs

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