Reducing FPGA Router Run-Time through Algorithm and Architecture

Gort, Marcel; Anderson, Jason

doi:10.1109/fpl.2011.67

Cited by 10 publications

(4 citation statements)

References 20 publications

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“…While a reduction in the the total number of iterations results into reduction of the computational runtime (hence this strategy can be seen as an alternative to [16] to reduce runtime), in this case, the reduction is overwhelmed by the runtime spent on constructing and solving the MCF problem.…”

Section: Discussion and Future Workmentioning

confidence: 99%

Net reordering and multicommodity flow based global routing for FPGAs

Ababei

Kavasseri

Zare

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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The most popular algorithm for solving the routing problem for field programmable gate arrays (FPGAs) has virtually remained the same for the past two decades. It is essentially an iterative maze technique, such as Dijkstra's algorithm, applied to each net in the circuit repeatedly. During multiple routing iterations, nets are ripped-up and rerouted via different paths to resolve competition for routing resources or to improve circuit delay. The most popular implementation of such a routing approach is the PathFinder algorithm used inside the VPR tool [1]. The quality of the routing solution depends however on the order in which nets are processed during each of the routing iterations. This is commonly referred to as the net ordering problem. PathFinder addresses this problem through continuous updates of the cost associated with overusing routing resources. After each routing iteration, the cost of overusing a routing resource is increased based on the routing so far, so that probability of resolving all congestion during future iterations increases.To further address the net ordering problem, in this paper, we investigate the effectiveness of two combined techniques to enhance PathFinder. We change the order in which nets are ripped-up and rerouted to give higher priority to nets with two, three, and more than eleven pins because these nets have the largest impact on the quality of the routing solution. Also, we alter the cost calculation during wave expansions for two-pin nets based on the global routing solution obtained by solving an equivalent multicommodity flow problem. Preliminary results suggest that the conventional FPGA routing solutions can still be improved.

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Section: Discussion and Future Workmentioning

confidence: 99%

Net reordering and multicommodity flow based global routing for FPGAs

Ababei

Kavasseri

Zare

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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“…Routing algorithms can be classified according to the algorithmic approach and to their cost function. From the algorithmic point of view, the geometric routing approach has been individuated as one of the most effective for FPGA routing [22]. Among this category of algorithms, the most used are the Maze Router, the A * Search and the Pathfinder [23].…”

Section: State Of the Artmentioning

confidence: 99%

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

Bozzoli

Sterpone

2020

IEEE Access

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Reconfigurable SRAM-based Field Programmable Gate Arrays (FPGAs) are everyday more attractive due to their high integration, performance, flexibility, and upgradability. Run-time reconfiguration improves the reconfigurable computing paradigm allowing to rewrite just a portion of the FPGA configuration memory on-line. This enhances the flexibility and provides opportunities for new high-performing architectures able to adjust in-flight the hardware to the current payload. However, the performance of reconfigurable architectures is bounded by the efficiency of the reconfiguration procedure, which in turn is bounded by the amount of configuration frames to be rewritten in the memory. Furthermore, the lack of tools and design software to implement optimized reconfigurable architectures makes their performance less efficient than expectation. In this work, we propose an approach to enhance the performance of reconfigurable systems by reducing the reconfiguration time of reconfigurable resources. Our method is based on a frame-driven routing algorithm able to drastically reduce the number of configuration memory frames used in the design. We evaluate the optimization achieved with our algorithm on several benchmark circuits of different size and we investigate the performance and the routability for different placement solutions. Experimental results confirm that our approach reduces the reconfiguration time up to 40% with respect to traditional reconfiguration approaches for a wide range of circuits.

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“…Techniques that accelerate core CAD algorithms can bring about important changes in product design times for these applications, whereas many designers may be willing to trade off some quality of the solution for an improved runtime of the CAD tools. Towards this goal, a number of algorithms have been proposed in the last years, spanning from fast application's placement [Wu and McElvain 2012], routing [Gort and Anderson 2011], as well as FPGA programming [Silva and Ferreira 2008]. Another challenging task for these algorithms affects the device fragmentation, as it introduces constraints to the performance of upcoming applications.…”

Section: Introductionmentioning

confidence: 99%

Jitpr

Sidiropoulos

Siozios

Figuli

et al. 2013

ACM Trans. Reconfigurable Technol. Syst.

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The execution runtime usually is a headache for designers performing application mapping onto reconfigurable architectures. In this article we propose a methodology, as well as the supporting toolset, targeting to provide fast application implementation onto reconfigurable architectures with the usage of a Just-In-Time (JIT) compilation framework. Experimental results prove the efficiency of the introduced framework, as we reduce the execution runtime compared to the state-of-the-art approach on average by 53.5×. Additionally, the derived solutions achieve higher operation frequencies by 1.17×, while they also exhibit significant lower fragmentation ratios of hardware resources.

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Reducing FPGA Router Run-Time through Algorithm and Architecture

Cited by 10 publications

References 20 publications

Net reordering and multicommodity flow based global routing for FPGAs

Net reordering and multicommodity flow based global routing for FPGAs

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

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