An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

Bozzoli, Ludovica; Sterpone, Luca

doi:10.1109/access.2020.2978632

Cited by 2 publications

(2 citation statements)

References 33 publications

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“…In the conventional memory architecture design, full supply voltage is used in the write, read, and hold operations [16], where the leakage power of the overall chip is increased due to full supply voltage [20]. Thus, an on-chip adaptive VDD scaled architecture is proposed in [17], which reduces the leakage power of the entire unselected rows using the supply selection circuit.…”

Section: Proposed Reconfigurable Vdd (R-vdd) Scaled Memory Architecturementioning

confidence: 99%

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

et al. 2021

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This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

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Section: Proposed Reconfigurable Vdd (R-vdd) Scaled Memory Architecturementioning

confidence: 99%

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

et al. 2021

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“…Unlike the Application Specific Integrated Circuits (ASICs), which are customized by the manufacturer, the FPGA is configured in the field by the user. The CLBs and RAMs are used to implement combinational and sequential logic functions in FPGAs [1,2]. Furthermore, certain FPGAs are partially reprogrammed in the runtime to perform the implementation of reconfigurable hardware circuits.…”

Section: Introductionmentioning

confidence: 99%

A Universal BIST Approach for Virtex-Ultrascale Architecture

Sathiabama¹,

Anila²

2023

Computer Systems Science and Engineering

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Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs' capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.

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An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

Cited by 2 publications

References 33 publications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

A Universal BIST Approach for Virtex-Ultrascale Architecture

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