A single capacitor bootstrapped power efficient CMOS driver

García, José Regidor; Montiel–Nelson, Juan A.; Nooshabadi, Saeid

doi:10.1109/mwscas.2005.1594095

“…Freewheeling diodes D 2 , D 3 , D 5 , and D 6 are connected to the source and drain of NMOSs, which will protect the NMOSs from the reverse current produced by their sudden shutdown. According to the command of the complex programmable logic device (CPLD), bootstrap gate drivers BGD 1 and BGD 2 control the on-off function of the NMOS by adjusting V gs (NMOS gate–source voltage) [ 8 , 9 ].…”

Section: Acoustic Emission Technique For Reducing Blind Zonementioning

confidence: 99%

Acoustic Emission and Echo Signal Compensation Techniques Applied to an Ultrasonic Logging-While-Drilling Caliper

Yao

¹

,

Ju

²

,

Lu

³

et al. 2017

Sensors

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A logging-while-drilling (LWD) caliper is a tool used for the real-time measurement of a borehole diameter in oil drilling engineering. This study introduces the mechanical structure and working principle of a new LWD caliper based on ultrasonic distance measurement (UDM). The detection range is a major performance index of a UDM system. This index is determined by the blind zone length and remote reflecting interface detection capability of the system. To reduce the blind zone length and detect near the reflecting interface, a full bridge acoustic emission technique based on bootstrap gate driver (BGD) and metal-oxide-semiconductor field effect transistor (MOSFET) is designed by analyzing the working principle and impedance characteristics of a given piezoelectric transducer. To detect the remote reflecting interface and reduce the dynamic range of the received echo signals, the relationships between the echo amplitude and propagation distance of ultrasonic waves are determined. A signal compensation technique based on time-varying amplification theory, which can automatically change the gain according to the echo arrival time is designed. Lastly, the aforementioned techniques and corresponding circuits are experimentally verified. Results show that the blind zone length in the UDM system of the LWD caliper is significantly reduced and the capability to detect the remote reflecting interface is considerably improved.

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“…In addition to the conventional bootstrapped driver, several bootstrapped driver designs have been reported [6][7][8][9][10]. The bootstrapped driver designs in [6] and [7] utilize pre-charged capacitors to couple the output loading charges directly, thus incurring a large area overhead, as the capacitors have to be sized in proportion to the large output loading.…”

Section: Introductionmentioning

confidence: 99%

“…The bootstrapped driver designs in [6] and [7] utilize pre-charged capacitors to couple the output loading charges directly, thus incurring a large area overhead, as the capacitors have to be sized in proportion to the large output loading. The area overhead is exacerbated by the fact that a capacitor implemented with a MOS structure has quite a poor area efficiency (low capacitance per unit area) at a low voltage subthreshold operation.…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

Lu

¹

,

Chuang

²

2012

JLPEA

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This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%-50% and a falling-delay improvement of 25%-47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%-43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.

show abstract

“…In addition to the conventional bootstrapped driver, several bootstrapped driver designs have been reported [6][7][8][9][10]. The bootstrapped driver designs in [6] and [7] utilize pre-charged capacitors to couple the output loading charges directly, thus incurring a large area overhead, as the capacitors have to be sized in proportion to the large output loading. The area overhead is exacerbated by the fact that a capacitor implemented with a MOS structure has quite a poor area efficiency (low capacitance per unit area) at a low voltage subthreshold operation.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

Lu

¹

,

Chuang

²

2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

1

0

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This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%-50% and a falling-delay improvement of 25%-47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%-43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.

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A single capacitor bootstrapped power efficient CMOS driver

Cited by 5 publications

References 11 publications

Acoustic Emission and Echo Signal Compensation Techniques Applied to an Ultrasonic Logging-While-Drilling Caliper

Acoustic Emission and Echo Signal Compensation Techniques Applied to an Ultrasonic Logging-While-Drilling Caliper

Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI

Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

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