A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature

Shimamura, K.; Takehara, T.; Shima, Yosuke; Tsunedomi, Kunihiko

doi:10.1109/prdc.2006.14

Cited by 10 publications

(10 citation statements)

References 9 publications

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“…1 (a) depicts the proposed comparison SRAM for the DMR system. In the conventional systems [1], all input/output are stored to "data to be compared" (DC); then the coherence is verified by a data comparator. The DC and data comparator can be replaced with the proposed comparison 7T SRAM block.…”

Section: T Comparison Sram Structure and Its Applicationmentioning

confidence: 99%

“…By using advanced process technology, redundant modules are integrated in a single chip, which can detect transient errors. The dual modular redundancy (DMR) adopted on chip multi processors (CMPs) is one method for improving the dependability [1,2,3,4]. There are three requirements for the DMR as key design [3].…”

Section: Introductionmentioning

confidence: 99%

“…Finally, the outputs are checked if the execution results are correct. The number of comparison cycles for the input/output data between the dual cores increases with the data size; the cycle overhead degrades the processor performance [1]. The memory bandwidth for the comparison is also a problem in the DMR systems.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Okumura¹,

Nakata²,

Yanagida³

et al. 2012

IEICE Electron. Express

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This paper proposes a 7T SRAM that realizes a blocklevel instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0 ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

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Section: T Comparison Sram Structure and Its Applicationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Okumura¹,

Nakata²,

Yanagida³

et al. 2012

IEICE Electron. Express

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show abstract

“…In previous studies, to realize self-checking or fail-safe LSIs, on-chip redundancy (namely, redundant subsystems within a chip for detecting error), self-checking comparator and optimal time diversity techniques [4] were proposed, and a prototype LSI was fabricated [5], [6]. In addition, safety microcontrollers have been commercially launched by several vendors [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?

Kanekawa

2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper investigates potential to improve faultdetection coverage by means of on-chip redundancy. The international standard on functional safety, namely, IEC61508 Ed. 2.0 Part 2 Annex E.3 prescribes the upper bound of β IC (common cause failure (CCF) ratio to all failures) is 0.25 to satisfy frequency upper bound of dangerous failure in the safety function for SIL (Safety Integrated Level) 3. On the other hand, this paper argues that the β IC does not necessarily have to be less than 0.25 for SIL 3, and that the upper bound of β IC can be determined depending on failure rate λ and CCF detection coverage. In other words, the frequency upper bound of dangerous failure for SIL3 can also be satisfied with β IC higher than 0.25 if the failure rate λ is lower than 400 [fit]. Moreover, the paper shows that on-chip redundancy has potential to satisfy SIL 4 requirement; the frequency upper bound of dangerous failure for SIL4 can be satisfied with feasible ranges of β IC , λ and CCF coverage which can be realized by redundant code.

show abstract

“…By using advanced process technology, redundant modules are integrated in a single chip, which can detect transient errors. The dual modular redundancy (DMR) adopted on chip multi processors (CMPs) is one method for improving the dependability [1][2][3][4]. There are three requirements for the DMR as key design [3].…”

Section: Introductionmentioning

confidence: 99%

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

Okumura

Nakata

Yanagida

et al. 2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

View full text Add to dashboard Cite

This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.

show abstract

A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature

Cited by 10 publications

References 9 publications

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?

Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy

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