A single-chip solution for an ADM-1/TMX-1 SDH telecommunication node element

Thalmann, M.; Stadler, M.; Röwer, T.; Felber, N.; Fichtner, W.

doi:10.1109/asic.1999.806493

Cited by 1 publication

(1 citation statement)

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“…The final target implementation was a O.5llm three-layer CMOS gate array. Thalmann et al (1999) report an architecture of an Add-OroplTerminal-Multiplexer for SOH, allowing to integrate all digital functions into one ASIC [17]. The idea is based in two approaches: buffer usage optimization and embedded processor, which substitutes various large hardware blocks.…”

Section: Related Workmentioning

confidence: 99%

Design and Protityping of an SDH-E1 Mapper Soft-Core

MarconI¹,

Palrna²,

Calazans³

et al. 2005

Journal of Communication and Information Systems

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This paper describes the design and prototyping of EMS, a telecommunication intellectual property soft-core developed in the scope of industry-academia cooperation. EMS performs insertion (mapping) and extraction (demapping) of EI channels into/from Synchronous Digital Hierarchy (SDH) frames. The basic SDH frame is transmitted in 155.52 Mbps rate, allowing to pack up to sixty-three 2.048 Mbps El channels. El channels belong to the Plesiochronous Digital Hierarchy (PDH). The paper addresses the solution of several synchronization problems implied by the El channels mapping/demapping process. EMS was fully described in RTL VHDL. It was functionally validated by simulation and prototyped in FPGA platforms. Together with the exploration of the techniques involved in embedding PDH into SDH frames, another contribution of the work is the availability of a reusable and parameterizable telecom core with high performance, low latency, and small size. Keywords-SDH, EI, SDH-EI mapping/demapping, soft IP core. Resumo-Este trabalho descreve 0 projeto e prototipa~ao do nucleo de propriedade intelectual para telecomunica~6es chamado EMS, que foi desenvolvido no escopo de uma coopera~ao Universidade-Empresa. EMS realiza a inser~ao/remo~ao de canais El ern/de quadros SDH (Synchronous Digital Hierarchy). 0 quadro basico SDH e transmitido em uma taxa de 155.52 Mbps, perrnitindo empacotar ate 63 canais El (2.048 Mbps). Os canais El pertencem a hierarquia digital plesiocrona (PDH). 0 trabalho trata da solu~ao de diversos problemas gerados pelo processo de inser~ao/remo~ao de canais El. EMS foi completamente descrito em RTL VHDL, foi validado funcionalmente por simula~ao e prototipado em plataformas FPGAs. Junto com a explora~ao de tecnicas que envolvem o empacotamento de PDH em quadros SDH, outra contribui~ao deste trabalho esta na disponibilidade de reutilizar e parametrizar urn nucleo de telecomunica~ao com alto desempenho, baixa latencia e tamanho pequeno. This work was supported by PUCRS University and Parks SA in the scope of an industry-academia cooperation. Authors I and 2 are PhD. students of Federal University of Rio Grande do SuI (UFRGS)-Porto Alegre-Rio Grande do Sui, Brazil-emails:{marcon.jcspalma}@inf.ufrgs.br. Authors 3 and 4 are professors of Pontifical Catholic University of Rio Grande do Sui (PUCRS)-Porto Alegre-Rio Grande do Sui, Brazil-emails{calazans.moraes}@inf.pucrs.br. Editor, networking area for Revista SBrT: Eduardo W. Bergamini.

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Section: Related Workmentioning

confidence: 99%