A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links

Zazo, Jose Fernando; López-Buedo, Sergio; Ruiz, Mario; Sutter, Gustavo

doi:10.1109/reconfig.2017.8279770

Cited by 9 publications

(5 citation statements)

References 10 publications

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“…A hardware implementation of CS [32] on a Xilinx Virtex Ultrascale XCVU095 FPGA uses an 8 ⇥ 1M sketch that achieves an average frequency estimate error of 1.29% on network data, while our own work achieves 0.12% error on the same data with a much smaller (4 ⇥ 16K) sketch. Both can operate at a line rate of 100Gbps.…”

Section: Discussionmentioning

confidence: 99%

“…Another [31] uses a 4 ⇥ 16K sketch on a Xilinx Virtex II XC2V1000 FPGA to perform feature extraction on network traffic data. More recently, an FPGA implementation of CS for heavy-hitter detection [32] is capable of operating at line rate on 100 Gbps Ethernet links using a 8⇥1M-counter sketch on a Xilinx Virtex UltraScale FPGA. Additionally, another hardware accelerator focuses on network traffic using sketches with the CM and K-ary algorithms [29], enabling heavy-hitter detection on a 150 Gbps link with a 5 ⇥ 32K-counter sketch.…”

Section: Related Workmentioning

confidence: 99%

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Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

et al. 2020

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Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a Field-Programmable Gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset. INDEX TERMS discriminative k-mers, heavy hitters, counting sketches, parallel processing, hardware acceleration, field-programmable gate arrays.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

et al. 2020

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“…This does not directly fit into the top‐ k problem, which assumes no prior knowledge of the items in the stream. This issue was addressed in the FPGA accelerator presented in [25], which adds an extra component at the output of the sketch referred to as a ‘priority queue’. This priority queue is basically a sorted list of the top‐ k items maintained in a RAM block.…”

Section: Related Workmentioning

confidence: 99%

Fast approximation of the top‐k items in data streams using FPGAs

Ebrahim

Khalifat

2023

IET Computers & Digital Tech

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Two methods are presented for finding the top-k items in data streams using Field Programmable Gate Arrays (FPGAs). These methods deploy two variants of a novel accelerator architecture capable of extracting an approximate list of the topmost frequently occurring items in a single pass over the input stream without the need for random access. The first variant of the accelerator implements the well-known Probabilistic sampling algorithm by mapping its main processing stages to a hardware architecture consisting of two custom systolic arrays. The proposed architecture retains all the properties of this algorithm, which works even if the stream size is unknown at run time.The architecture shows better scalability compared to other architectures that are based on other stream algorithms. In addition, experimental results on both synthetic and real datasets, when implementing the accelerator on an Intel Arria 10 GX 1150 FPGA device, showed very good accuracy and significant throughput gains compared to the existing software and hardware-accelerated solutions. The second variant of the accelerator is specifically tailored for applications requiring higher accuracy, provided that the size of the stream is known at run time. This variant takes advantage of the embedded memory resources in an FPGA to implement a sketch-based filter that precedes the main systolic array in the accelerator's pipeline. This filter enhances the accuracy of the accelerator by pre-processing the stream to remove much of the insignificant items, allowing the accelerator to process a significantly smaller filtered stream.

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“…Finally, the network community has also proposed several FPGAaccelerated sketching approaches for network monitoring [18,20,21,23,24,29]. These approaches assume that only a few fields of each package need to be processed, and thus it is sufficient to process a single value per clock cycle.…”

Section: Related Workmentioning

confidence: 99%

Optimistic Data Parallelism for FPGA-Accelerated Sketching

et al. 2023

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Sketches are a popular approximation technique for large datasets and high-velocity data streams. While custom FPGA-based hardware has shown admirable throughput at sketching, the state-of-the-art exploits data parallelism by fully replicating resources and constructing independent summaries for every parallel input value. We consider this approach pessimistic, as it guarantees constant processing rates by provisioning resources for the worst case. We propose a novel optimistic sketching architecture for FPGAs that partitions a single sketch into multiple independent banks shared among all input values, thus significantly reducing resource consumption. However, skewed input data distributions can result in conflicting accesses to banks and impair the processing rate. To mitigate the effect of skew, we add mergers that exploit temporal locality by combining recent updates. Our evaluation shows that an optimistic architecture is feasible and reduces the utilization of critical FPGA resources proportionally to the number of parallel input values. We further show that FPGA accelerators provide up to 2.6 x higher throughput than a recent CPU and GPU, while larger sketch sizes enabled by optimistic architectures improve accuracy by up to an order of magnitude in a realistic sketching application.

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A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links

Cited by 9 publications

References 10 publications

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

Fast approximation of the top‐k items in data streams using FPGAs

Optimistic Data Parallelism for FPGA-Accelerated Sketching

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