A single-poly EEPROM cell structure compatible to standard CMOS process

Lin, Chih-Che; Sun, Chih-Ming

doi:10.1016/j.sse.2007.05.001

Cited by 12 publications

(1 citation statement)

References 9 publications

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“…The controllability of the floating gate (FG) transistor threshold voltage shift could provide solutions to overcome some of these challenges and can be further explored in tuning circuits, switching circuits and also in millimetre-wave application, among other applications (Mabuza et al, 2009). Different FG structures have been proposed in literature (Raguet et al, 2008;Di Bartolomeo et al, 2009;Lin and Sun, 2007;Bouchakour et al, 2001).…”

Section: Introductionmentioning

confidence: 99%

The tunnelling and electron injection reliabilities for FG transistors

Mabuza

Sinha

2014

Microelectronics International

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Purpose -The purpose of this paper was to present the results of the three types of FG transistors that were investigated.The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG). Approach -The tunnelling and electron injection methods were applied to program FG devices of different length (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology. Findings -Current leakages are increasing with device scaling and reduce the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered. Originality/value -Although the results have raised further research questions, as revealed by certain reliability issues, the results have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

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Section: Introductionmentioning

confidence: 99%

The tunnelling and electron injection reliabilities for FG transistors

Mabuza

Sinha

2014

Microelectronics International

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Design of 512-bit logic process-based single poly EEPROM IP

Jin

Jang

et al. 2011

J. Cent. South Univ. Technol.

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A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 µm 2 , about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC−DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 µm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 µW, respectively, and the EEPROM size is 0.12 mm 2 .

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