A soft processor overlay with tightly-coupled FPGA accelerator

Ng, Ho-Cheung; Cheng, Liu; So, Hayden Kwok-Hay

doi:10.5353/th_b5760970

Cited by 6 publications

(5 citation statements)

References 20 publications

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“…There are also numerous FPGA-based vector processors and overlays, but are not suitable for exploring modular SIMD instructions for CPUs. Example limitations include the need to pass exclusive control to dedicated accelerator logic [28], fixed vector instruction sets [29]- [33], absence of base instruction set [34] or complete absence of instructions [35].…”

Section: Related Workmentioning

confidence: 99%

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

Papaphilippou

Paul

Luk

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the design's memory system is optimised for streaming bandwidth, such as very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications with custom instructions. This paper also provides insights on the effectiveness of adding FPGA resources in general purpose processors in the form of reconfigurable SIMD instructions.

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Section: Related Workmentioning

confidence: 99%

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

Papaphilippou

Paul

Luk

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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“…The overlay architecture proposed by Ng et al [8] consists of a RISC-V-based soft-core with ISA extensions to implement runtime transfer of control to a tightly-coupled hardware accelerator. Similar to our work, the authors demonstrate that hybrid software-hardware applications achieve comparable performance to pure-hardware implementations.…”

Section: Background a Related Workmentioning

confidence: 99%

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

Bellocchi

Capotondi

Conti

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

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Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. FPGA-based HeSoCs can reach high performance and energy efficiency at the cost of increased design complexity. High-Level Synthesis (HLS) can ease IP design, but automated tools still lack the maturity to efficiently and easily tackle systemlevel integration of the many hardware and software blocks included in a modern CPS. We present an innovative hardware overlay offering plug-and-play integration of HLS-compiled or handcrafted acceleration IPs thanks to a customizable wrapper attached to the overlay interconnect and providing shared-memory communication to the overlay cores. The latter are based on the open RISC-V ISA and offer simplified software management of the acceleration IP. Deploying the proposed overlay on a Xilinx ZU9EG shows ≈ 20% LUT usage and ≈ 4× speedup compared to program execution on the ARM host core.

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“…The hardware acceleration described in [2] is achieved connecting the accelerator to the bus or crossbar so that no change to the ISA is required (as is typically done on Zynq platforms). The extendability of RISC-V enables ISA application-specific extensions to increase performance in a specific application for tightly coupled accelerators, as described in [64]. Also this approach has a high cost, especially because it makes reuse of the software ecosystem more difficult Fig.…”

Section: Processors To Enable On-board Decision Makingmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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A soft processor overlay with tightly-coupled FPGA accelerator

Cited by 6 publications

References 20 publications

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

Leveraging the Openness and Modularity of RISC-V in Space

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