Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

Papaphilippou, Philippos; Paul, H J Kelly; Luk, Wayne

doi:10.1109/fpl53798.2021.00082

Cited by 7 publications

(6 citation statements)

References 38 publications

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“…The memory hierarchy tends to always favour CPU performance, hence the presence of expensive off-chip memories in high-end FPGA boards. This heterogeneity is considered to impact FPGA development, as well as to increase the cost and deployment of FPGAs in the datacenter [21].…”

Section: A Current Cpu and Fpga Systemsmentioning

confidence: 99%

“…Simodense [21] is a RISC-V softcore that allows specialisation with custom SIMD instructions of custom pipeline lengths. Although this framework is targeted for exploring FPGAs as instructions [19], it does not elaborate on system architecture.…”

Section: Related Workmentioning

confidence: 99%

“…For evaluating of our proposal, an open-source FPGAoptimised softcore [21] is extended, that originally supported the RV32IM specification, where the "RV32I" part is the base 32-bit integer instruction set, and "M" is the extension for integer multiplication and division [2]. The instructions of the latter extension occupy 4 (non-blocking) cycles of latency [21].…”

Section: A Simulated Hardwarementioning

confidence: 99%

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FPGA-extended Modified Harvard Architecture

Papaphilippou¹,

Shah²

2022

Preprint

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This paper explores a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). It has already been demonstrated that small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom instructions and, in some cases, approach accelerator-level of performance. Our proposed architecture goes one step further to directly address some related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, including access to the memory hierarchy with the highest bandwidth available. The main contribution is the introduction of the "FPGA-extended modified Harvard architecture" model to enable context-switching between processes with a different distribution of instructions without modifying the applications. The cycle-approximate evaluation of a dynamically reconfigurable core shows promising results for multi-processing, approaching the performance to an equivalent core with all enabled instructions, and better performance than when featuring a fixed subset of the supported instructions.

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Section: A Current Cpu and Fpga Systemsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: A Simulated Hardwarementioning

confidence: 99%

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FPGA-extended Modified Harvard Architecture

Papaphilippou¹,

Shah²

2022

Preprint

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“…Due to the open-source RISC-V softcore design flexibility, it is being used in many applications. Researchers are able to integrate customized SIMD instructions and optimize microarchitecture to increase the efficiency of the processor [54], [55]. The RISC-V V-extension (RVV) is meant for highperformance cores and provides support for 8-bit, 16-bit, and 32-bit integer SIMD instructions.…”

Section: Introductionmentioning

confidence: 99%

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

Mustafa,

Alkhasawneh,

Obeidat

et al. 2024

IEEE Access

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The Single Instruction Multiple Data (SIMD) architecture, supported by various highperformance computing platforms, efficiently utilizes data-level parallelism. The SIMD model is used in traditional CPUs, dedicated vector systems, and accelerators such as GPUs, vector extensions, and Xeon Phi. It provides performance throughput in computation-intensive and data-parallel applications. Despite the similarity of data-processing principles between these architectures, porting various programming models between the reviewed platforms is challenging. Furthermore, enhancing the programmability of these architectures is an important feature for utilizing their emerging computing power and simplifying programming complexity. This paper reviews the basic principles of optimization techniques to run asynchronous Multiple Instruction Multiple Data (MIMD) on SIMD accelerators. It also surveys several GPU programming paradigms and application programming interfaces (APIs) and classifies these frameworks into different groups based on their criteria. In addition, a review of studies that performed a comparison of the collaborative execution of GPUs with CPUs and Xeon Phi is presented in this paper. This study will be beneficial for developers and researchers in the field of computer architecture and parallel computing of intensive scientific applications, specifically for early-stage high-performance computing researchers, to obtain a brief overview of performance optimization opportunities as well as the challenges of existing SIMD platforms.

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“…In combination with the openness of the RISC-V instruction set, and its support for custom instructions, now is an appropriate time to explore reconfigurable SIMD instructions, as demonstrated here with the use of the proposed open-source 1 RISC-V-based softcore [3].…”

mentioning

confidence: 99%

Demonstrating custom SIMD instruction development for a RISC-V softcore

Papaphilippou

Luk

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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This demo elaborates on the programmability aspect of Simodense, a recently released open-source softcore, optimised for evaluating custom SIMD instructions. CPUs featuring small reconfigurable areas for implementing custom instructions is an alternative path in computer architecture that can help with the challenges found in today's FPGAs. By providing RTL-based programmability for implementing custom SIMD instructions, highly-integrated accelerators can be developed, while benefiting from the pre-existing CPU logic, such as the caches and their high memory throughput to main memory.

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Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

Cited by 7 publications

References 38 publications

FPGA-extended Modified Harvard Architecture

FPGA-extended Modified Harvard Architecture

MIMD Programs Execution Support on SIMD Machines: A Holistic Survey

Demonstrating custom SIMD instruction development for a RISC-V softcore

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