FPGA-extended Modified Harvard Architecture

Abstract

This paper explores a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). It has already been demonstrated that small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom instructions and, in some cases, approach accelerator-level of performance. Our proposed architecture goes one step further to directly address some related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, including access to the memory hierarchy with the highest bandwidth available. The main contribution is the introduction of the "FPGA-extended modified Harvard architecture" model to enable context-switching between processes with a different distribution of instructions without modifying the applications. The cycle-approximate evaluation of a dynamically reconfigurable core shows promising results for multi-processing, approaching the performance to an equivalent core with all enabled instructions, and better performance than when featuring a fixed subset of the supported instructions.

Arch-Lang : A DSE Tool for Flexible Hardware/Software Co-Design

“…Variables are held in isolation from both code memory and the execution stack, and are implemented as a linked-list of name-value mappings. This isolation of instruction memory from data memory is not dissimilar from a Harvard architecture [58] [59], as opposed to the von Neumann architecture which combines both data and instruction memory.…”