A software-based self test of CUDA Fermi GPUs

Carlo, Stefano Di; Gambardella, Giulio; Indaco, Marco; Martella, Ippazio; Prinetto, P.; Rolfo, Daniele; Trotta, Pascal

doi:10.1109/ets.2013.6569353

Cited by 35 publications

(11 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The overall approach requires the knowledge of the full map of faulty SMs. Faulty SMs can be identified by periodically running functional test procedures on the GPU, such as the one proposed in [17]. This activity is out of the scope of this paper that focuses on the mitigation of these faults.…”

Section: Proposed Fault Mitigation Methodologymentioning

confidence: 99%

Fault mitigation strategies for CUDA GPUs

Carlo

Gambardella

Martella

et al. 2013

2013 IEEE International Test Conference (ITC)

Self Cite

View full text Add to dashboard Cite

High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents effective fault mitigation strategies for CUDA-based GPUs against permanent faults. The methodology to apply these strategies, on the software to be executed, is fully described and verified. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementation, even in presence of multiple permanent faults.

show abstract

Section: Proposed Fault Mitigation Methodologymentioning

confidence: 99%

Fault mitigation strategies for CUDA GPUs

Carlo

Gambardella

Martella

et al. 2013

2013 IEEE International Test Conference (ITC)

Self Cite

View full text Add to dashboard Cite

show abstract

“…A few works proposed methods aimed to test of GPGPU-based systems. In [30], the authors adapted the CPU testing techniques to GPUs using a high-level programming language approach and combining pseudo-assembly instructions to test the integer and the floating execution units in the Streaming Multiprocessor (SM) cores. Moreover, the same method was partially applied to functionally test the special function units (SFUs) in the GPGPUs.…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

View full text Add to dashboard Cite

The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

show abstract

“…Researches have also investigated the possibility of using software-based self-test (SBST) programs in order to detect and localize permanent faults in GPGPUs: a preliminary work proposing a possible SBST solution has been presented in [13].…”

Section: Related Workmentioning

confidence: 99%

Reliability Evaluation of Embedded GPGPUs for Safety Critical Applications

Sabena

Sterpone

Carro

et al. 2014

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Thanks to the capability of efficiently executing massive computations in parallel, general purpose graphic processing units (GPGPUs) have begun to be preferred to CPUs for several parallel applications in different domains. Two are the most relevant fields in which, recently, GPGPUs have begun to be employed: high performance computing (HPC) and embedded systems. The reliability requirements are different in these two applications domain. In order to be employed in safety-critical applications, GPGPUs for embedded systems must be qualified as reliable. In this paper, we analyze through neutron irradiation typical parallel algorithms for embedded GPGPUs and we evaluate their reliability. We analyze how caches and threads distributions affect the GPGPU reliability. The data have been acquired through neutron test experiments, performed at the VESUVIO neutron facility at ISIS. The obtained experimental results show that, if the L1 cache of the considered GPGPU is disabled, the algorithm execution is most reliable. Moreover, it is demonstrated that during a FFT execution most errors appear in the stages in which the GPGPU is completely loaded as the number of instantiated parallel tasks is higher.

show abstract

A software-based self test of CUDA Fermi GPUs

Cited by 35 publications

References 20 publications

Fault mitigation strategies for CUDA GPUs

Fault mitigation strategies for CUDA GPUs

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

Reliability Evaluation of Embedded GPGPUs for Safety Critical Applications

Contact Info

Product

Resources

About