A Source and Channel Coding Approach for Improving Flash Memory Endurance

Freudenberger, Jürgen; Rajab, Mohammed; Shavgulidze, Sergo

doi:10.1109/tvlsi.2018.2797078

Cited by 7 publications

(12 citation statements)

References 41 publications

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“…Universal data compression for flash memory systems has recently gained interest [1][2][3][4][5][6][7][8][9] because data compression can improve the storage capacity and the flash memory lifetime. Compression of redundant data reduces the amount of data transferred from the host to the flash system.…”

Section: Introductionmentioning

confidence: 99%

“…This reduces the write amplification in flash memories, which is caused by the fact that the amount of data written to the flash memory is often much larger than the amount intended to be written [1,10]. Moreover, data compression can be utilised to improve the reliability of the non-volatile storage system [2,[5][6][7]9]. Data compression for such applications requires high data throughput that can only be achieved using hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

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Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

Safieh

Freudenberger

2019

IET Circuits, Devices & Systems

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The Lempel-Ziv-Welch (LZW) algorithm is an important dictionary-based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

Safieh

Freudenberger

2019

IET Circuits, Devices & Systems

Self Cite

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“…Data compression is an important component of many storage and communication systems. For instance, in flash memory systems data compression can improve the storage capacity and the flash memory lifetime [1][2][3][4][5][6][7][8][9]. Data compression can reduce the amount of data transferred from the host system.…”

Section: Introductionmentioning

confidence: 99%

“…This reduces the so-called write amplification in flash memories [1,8], which is caused by the fact that the amount of data written to the flash memory is frequently a multiple of the amount intended to be written. Moreover, data compression can be used to improve the error correction coding and the reliability of the non-volatile storage system [2,[5][6][7]9]. Data compression for such applications requires high data throughput that can only be achieved using hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

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Pipelined decoder for the limited context order Burrows–Wheeler transformation

Safieh

Freudenberger

2018

IET Circuits, Devices & Systems

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The Burrows-Wheeler transformation (BWT) is a reversible block sorting transform that is an integral part of many data compression algorithms. This work proposes a memory-efficient pipelined decoder for the BWT. In particular, the authors consider the limited context order BWT that has low memory requirements and enable fast encoding. However, the decoding of the limited context order BWT is typically much slower than the encoding. The proposed decoder pipeline provides a fast inverse BWT by splitting the decoding into several processing stages which are executed in parallel.

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Read Reference Voltage Adaptation for NAND Flash Memories With Neural Networks Based on Sparse Histograms

2023

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Non-volatile NAND flash memories store information as an electrical charge. Different read reference voltages are applied to read the data. However, the threshold voltage distributions vary due to aging effects like program erase cycling and data retention time. It is necessary to adapt the read reference voltages for different life-cycle conditions to minimize the error probability during readout. In the past, methods based on pilot data or high-resolution threshold voltage histograms were proposed to estimate the changes in voltage distributions. In this work, we propose a machine learning approach with neural networks to estimate the read reference voltages. The proposed method utilizes sparse histogram data for the threshold voltage distributions. For reading the information from triple-level cell (TLC) memories, several read reference voltages are applied in sequence. We consider two histogram resolutions. The simplest histogram consists of the zero-and-one ratios for the hard decision read operation, whereas a higher resolution is obtained by considering the quantization levels for soft-input decoding. This approach does not require pilot data for the voltage adaptation. Furthermore, only a few measurements of extreme points of the threshold voltage distributions are required as training data. Measurements with different conditions verify the proposed approach. The resulting neural networks perform well under other life-cycle conditions.INDEX TERMS Non-volatile NAND flash, channel estimation, machine learning, neural network, read reference adjustment.

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A Source and Channel Coding Approach for Improving Flash Memory Endurance

Cited by 7 publications

References 41 publications

Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

Pipelined decoder for the limited context order Burrows–Wheeler transformation

Read Reference Voltage Adaptation for NAND Flash Memories With Neural Networks Based on Sparse Histograms

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