A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation

Chen, Yingyu; Sangai, Amit; Rogachev, Artem; Gholipour, Morteza; Iannaccone, Giuseppe; Fiori, Gianluca; Chen, Deming

doi:10.1109/tnano.2015.2469647

Cited by 72 publications

(89 citation statements)

References 35 publications

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“…Important variations in the power (mainly static) of an inverter gate have been observed in simulation experiments [9,21,23,31].…”

Section: Ribbon Widthmentioning

confidence: 99%

“…In this section we show some examples of logic circuits based on GNR FET devices. Most of the logic circuits proposed in the literature [2, 10,13,21,23,24] present a CMOS-like structure. They are basic logic gates or memory cells.…”

Section: Graphene Nanoribbon Logic Circuitsmentioning

confidence: 99%

“…Note that our work is based on a qualitative analysis of fault propagation, using the equations of the devices and the structure of the logic circuits. Other research papers in the literature [21][22][23] have applied simulations at physical and electronic (SPICE) levels in a more quantitative approach. These two types of analysis may complement each other.…”

Section: Introductionmentioning

confidence: 99%

“…Important variations in the delay of an inverter gate have been observed in simulation experiments [21,23]. The delay increases notably as the width of the GNR decreases.…”

mentioning

confidence: 96%

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Fault Modeling of Graphene Nanoribbon FET Logic Circuits

et al. 2019

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Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

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“…Important variations in the power (mainly static) of an inverter gate have been observed in simulation experiments [9,21,23,31].…”

Section: Ribbon Widthmentioning

confidence: 99%

Section: Graphene Nanoribbon Logic Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Important variations in the delay of an inverter gate have been observed in simulation experiments [21,23]. The delay increases notably as the width of the GNR decreases.…”

mentioning

confidence: 96%

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Fault Modeling of Graphene Nanoribbon FET Logic Circuits

et al. 2019

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“…Graphene in its pristine 2-D form is semi-metallic and has no band gap. While band gap can be opened by narrowing graphene into graphene nanoribbons under 10 nm, issues such as process variation, mobility degradation, and line edge roughness severely degrade its performance [2][3][4][5][6][7][8]. TMDs, on the other hand, have a band gap of 1-2 eV by nature without scaling down to the small nanometer range, which greatly reduces the difficulty of production and also mitigates undesirable effects from process variation.…”

Section: Introductionmentioning

confidence: 99%

A SPICE model of flexible transition metal dichalcogenide field-effect transistors

Chen

Sun

Chen

2015

Proceedings of the 52nd Annual Design Automation Conference

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This paper presents the first SPICE model of the transition metal dichalcogenide (TMD) field-effect transistor (FET), which is a promising candidate for flexible electronics. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials (MoS 2 , WSe 2 , etc.), as well as the applied strain, which enables the evaluation of transistor-and circuit-level behavior under process variation and different levels of bending. We performed SPICE simulations on digital logic gates to explore the design space of both MoS 2 -and WSe 2 -based transistors, and to evaluate the projected performance of these circuits under applied strain. Our simulations show that WSe 2 circuits outperform MoS 2 and Si-based CMOS in terms of energy-delay product (EDP) by up to 1 order of magnitude, depending on applications. Finally, we investigate TMDFET's behavior under process variation.

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Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Madhuri

Sunithamani

2020

Circuit Theory & Apps

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This paper presents the investigations of crosstalk effects in ternary logic-based coupled interconnects. The crosstalk analysis is investigated for coupled copper interconnects and copper-multilayer graphene (Cu-MLG) interconnects. In Cu-MLG interconnects, the Cu interconnect is enclosed with MLG barrier and standard ternary inverter is used to drive the interconnect. Based on the industry standard HSPICE simulation results, the crosstalk effects such as noise peak and delay are lower compared with conventional Cu interconnects. Moreover, the Cu-MLG interconnects show reduced power dissipation, power delay product (PDP), and energy delay product (EDP) over the Cu interconnects. From the simulation results, it is observed that the Cu-MLG interconnects provides the performance improvements up to 30.67% compared with the Cu interconnects. Thus, the Cu-MLG interconnects are more compatible for ternary logic integrated circuits compared with traditional Cu interconnects.

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A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation

Cited by 72 publications

References 35 publications

Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Fault Modeling of Graphene Nanoribbon FET Logic Circuits

A SPICE model of flexible transition metal dichalcogenide field-effect transistors

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

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