A SRAM Memory Cell Design in FPGA

Abstract

The main objective of this work is to design a memory cell in Field Programmable Gate Array (FPGA) that consumes lesser power with reduced delay constraint. In the existing system, the FPGA is based on 10T Static Random Access Memory (SRAM) cell configuration in which power consumption is relatively high. The proposed work includes a Self controllable Voltage Level (SVL) circuit along with 10T SRAM cell and asynchronous counters in read circuit memory block instead of shift registers. The stand-by leakage power of 10T SRAM is reduced by incorporating a newly-developed leakage current reduction circuit called SVL circuit, with minimal overheads in terms of chip area and speed, which retains data in standby mode. In asynchronous counters, external clock is connected to the clock input of the first flip-flop only, whereas the successive flip-flops change when it is triggered by the falling edge of the previous counterparts. The various FPGA components are implemented in 180nm technology to evaluate the FPGA performance. Parameters like average power consumption and power delay product are compared with the existing system and it is found that the proposed system consumes lesser power but at the cost of the power delay product. The software tool used for design and simulation of various FPGA components is TANNER S-Edit. Keywords10T SRAM, FPGA, nm technology, Self controllable Voltage level circuit (SVL). 1.INTRODUCTIONPower consumption concerns came into play with the appearance of the first portable electronic systems in the late 1980s. In this market, the battery lifetime is a decisive factor for the commercial success of the product. Another fact that became apparent at about the same time was that the increasing integration of more active elements per die area would lead to prohibitively large-energy consumption of an integrated circuit. A high absolute level of power is not only undesirable for economic and environmental reasons, but it also creates the problem of heat dissipation. In order to keep the device working at acceptable temperature levels, excessive heat may require expensive heat removal systems. These factors have contributed to the rise of power as a major design parameter on par with performance and die size. In fact, power consumption is regarded as the limiting factor in the continuing scaling of CMOS technology. Low-power VLSI design is becoming a key issue in designing battery driven circuits, high performance digital systems and also for storage circuits. It is said that memories, the core section of digital circuits, are the major customers of power in any digital system. Memory blocks consist of Static Random Access Memory (SRAM) cells. The power consumption and speed of SRAMs are the two important issues to be considered while designing low power VLSI circuits. The power consumption of digital CMOS circuits is generally considered in terms of three components. They are 1) dynamic power component, related to the charging and discharging of the load capacitance at the gate output. 2...