2015 International Conference on Computer, Communication and Control (IC4) 2015
DOI: 10.1109/ic4.2015.7375605
|View full text |Cite
|
Sign up to set email alerts
|

A stable and power efficient SRAM cell

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
4
2

Relationship

0
6

Authors

Journals

citations
Cited by 8 publications
(1 citation statement)
references
References 5 publications
0
1
0
Order By: Relevance
“…When implementing this design in an array, due to the huge multiplying factor, the area of the overall memory chip increases considerably. [7] explores a 9T SRAM cell which includes Stacking and Dual Threshold voltage implementations to reduce leakage power. In [8], two SRAM cells are presented: one structure using NMOS pass transistors to reduce gate leakage current and the other structure using PMOS pass transistors.…”
Section: Introductionmentioning
confidence: 99%
“…When implementing this design in an array, due to the huge multiplying factor, the area of the overall memory chip increases considerably. [7] explores a 9T SRAM cell which includes Stacking and Dual Threshold voltage implementations to reduce leakage power. In [8], two SRAM cells are presented: one structure using NMOS pass transistors to reduce gate leakage current and the other structure using PMOS pass transistors.…”
Section: Introductionmentioning
confidence: 99%