A Stacked Capacitor Multi-Microwatts Source Energy Harvesting Scheme With 86 mV Minimum Input Voltage and &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;${\pm}3$&lt;/tex&gt;&lt;/formula&gt; V Bipolar Output Voltage

Teh, Ying-Khai; Mok, Philip K. T.

doi:10.1109/jetcas.2014.2337152

Cited by 11 publications

(2 citation statements)

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“…As pointed out in Sedra and Smith, 8 sometimes it is important to include a narrow hysteresis window to a comparator in order to avoid inappropriate output changes of the comparator due to interference signals of very‐high frequency. Another important application of comparators of narrow hysteresis is that of ripple‐based control of direct current–direct current (DC–DC) converters 9,10 …”

Section: Introductionmentioning

confidence: 99%

“…Due to the lack of a good model to determine the hysteresis window, several designers have either resorted to intensive simulation 10,11 to find out the appropriate size of the ST transistors or proposed ST architectures 12,13 that are amenable to adjustment. In fact, designers of integrated circuits still struggle to place correctly the thresholds of the CMOS ST, in spite of its use in present‐day applications 14 .…”

Section: Introductionmentioning

confidence: 99%

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Inadequacy of the classical formulation of the CMOS Schmitt trigger

Júnior

Melek²,

Galup-Montoro

et al. 2021

Circuit Theory & Apps

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Summary The classical complementary metal–oxide–semiconductor (CMOS) Schmitt trigger (ST) circuit operating in strong inversion has been used as a basic building block in electronics since the 70s. However, no appropriate analytical models for determining the hysteresis threshold voltages have been presented. In this paper, we review the classical CMOS ST formulation for operation in strong inversion and introduce a new model for calculating the hysteresis window. In order to validate the approximations employed in this work, we measured the hysteresis curve for several combinations of transistors available in the popular off‐the‐shelf CD4007 and resorted to simulation in a 180‐nm technology for the specific purpose of measuring the ST window in terms of the transistors aspect ratios. Numerical, experimental, and simulation results corroborate the approximations employed in this research to derive simple expressions for the hysteresis threshold voltages.

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Section: Introductionmentioning

confidence: 99%