A static low-power, high-performance 32-bit carry skip adder

Chirca, K.; Schulte, Michael; Glossner, John; Wang, Horan; Mamidi, B.; Balzola, P.I.; Vassiliadis, S.

doi:10.1109/dsd.2004.1333335

Cited by 30 publications

(16 citation statements)

References 10 publications

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“…This paper is a deviation from the tree approach presented in the ELM adder. A 32-bit adder implementation with a delay of 7 logic levels using carry-skip adders and ripple-carry adders was presented in [4]. This is shown in Figure 1.…”

Section: Vlsi Designmentioning

confidence: 99%

“…They are (i) 32-bit carry skip-adder proposed in [4] and (ii) 32-bit multilevel carry-skip adder proposed in [11]. The first one is referred here as Chirca adder and the second one is referred as Gayles adder.…”

Section: Simulationmentioning

confidence: 99%

“…In our design, the generatepropagate logic balances the delay and the number of inputs to the skip logic limits the critical path delay. By applying our design procedure, we speed up the adder by 18% when compared to the current fastest 32-bit adder [4]. In Section 2, we will discuss the previous work done in the area of highperformance adders.…”

Section: Introductionmentioning

confidence: 99%

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Delay Efficient 32‐Bit Carry‐Skip Adder

Lin

Radhakrishnan

2008

VLSI Design

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 μm CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.

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Section: Vlsi Designmentioning

confidence: 99%

Section: Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Delay Efficient 32‐Bit Carry‐Skip Adder

Lin

Radhakrishnan

2008

VLSI Design

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“…In addition, the power-delay product (PDP) of the CSKA is smaller than those of the CSLA and PPA structures [19]. In addition, due to the small number of transistors, the CSKA benefits from relatively short wiring lengths as well as a regular and simple layout [18]. The comparatively lower speed of this adder structure, however, limits its use for high-speed applications.…”

mentioning

confidence: 98%

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Bahadori

Kamal

Afzali-Kusha

et al. 2016

IEEE Trans. VLSI Syst.

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In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power-delay product was the lowest among the structures considered in this paper, while its energy-delay product was almost the same as that of the Kogge-Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.Index Terms-Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.

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“…Chirca et al K., [3] compared a carry skip adder by various existing logic styles. The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved.…”

Section: Introductionmentioning

confidence: 99%

An Optimized Design of High-Speed and Energy-Efficient Carry Skip Adder with Variable Latency Extension

2016

IJSR

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Abstract:The portable equipments such as cellular phones, Personal Digital Assistant (PDA), and notebook personal computer, arise the need of effective circuit area and power efficient VLSI circuits. Addition is the most common and often used arithmetic operation in digital computers and also, it serves as a building block for synthesis all other arithmetic operations. Low-power and high-speed adder cells (like carry skip adder) are used in battery operation based devices. Now the biggest challenge is reduction of adder power consumption and delay while maintaining the high performance in different types of circuit design. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer and also it containing twelve transistors that leads to increase of area usage and power consumption. The proposed method uses compound gates such as AOI and OAI as skip logic in the design that leads to decrease area usage, delay and power consumption, also in addition the parallel prefix adder is included to attain further reduction of power. The design is coded in VHDL and simulated in ModelSim and its area, delay and power are analyzed using Xilinx_ISE 9.2i.

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A static low-power, high-performance 32-bit carry skip adder

Abstract: In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation.

Cited by 30 publications

References 10 publications

Delay Efficient 32‐Bit Carry‐Skip Adder

Delay Efficient 32‐Bit Carry‐Skip Adder

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

An Optimized Design of High-Speed and Energy-Efficient Carry Skip Adder with Variable Latency Extension

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