A statistical approach for full-chip gate-oxide reliability analysis

Chopra,; Zhuo,; Blaauw,; Sylvester,

doi:10.1109/iccad.2008.4681653

Cited by 18 publications

(18 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Due to the extra process complexity required to build deeply scaled devices, the number of device parameters affected by inter-die and intra-die variations dramatically grows [13]. The variation modeling requires distinct variables for each physical and structural parameter in order to represent the effect of PV.…”

Section: Background and Motivationmentioning

confidence: 99%

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Mohammadi¹,

Gaillardon²,

Yazdani³

et al. 2014

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

View full text Add to dashboard Cite

Abstract-With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as Principal Component Analysis (PCA) and Independent Component Analysis (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on Double-Gate Silicon NanoWire FET (DG-SiNWFET) technology indicate 2.5× speed up in timing variation analysis of the ISCAS89-s27 benchmark with a controlled average error bound of 9.4%.

show abstract

Section: Background and Motivationmentioning

confidence: 99%

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Mohammadi¹,

Gaillardon²,

Yazdani³

et al. 2014

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

View full text Add to dashboard Cite

show abstract

“…For this problem, 0 ≤ p i ≤ 1 and 0 < µ i ≪ 1 7 . Thus the conditions |x| ≤ 1, x 1 for the Taylor expansion of ln(1 − x) are satisfied, and the approximations with first-order Taylor expansions are quite accurate since the high order terms O(x 2 ) are much smaller.…”

Section: Appendixmentioning

confidence: 99%

“…Thus the conditions |x| ≤ 1, x 1 for the Taylor expansion of ln(1 − x) are satisfied, and the approximations with first-order Taylor expansions are quite accurate since the high order terms O(x 2 ) are much smaller. We can convert Equation (21) to the following form: 7 The concerned circuit failure is usually at the low end, e.g. P f < 0.1.…”

Section: Appendixmentioning

confidence: 99%

“…The idea is based on the weakest-link assumption, that the failure of any individual device will cause the failure of the whole chip. Recently, new approaches have been proposed to improve the prediction accuracy by empirical calibration using real circuit test data [6], or by considering the variation of gate-oxide thickness [7]. The former is empirical and hard to generalize, while the latter does not consider the effect of breakdown location.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Scalable methods for the analysis and optimization of gate oxide breakdown

Fang

Sapatnekar

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11× relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.

show abstract

“…Memory effects have been addressed in [10]. For logic circuits, a conventional area-scaling based method is presented in [11]. However, it has been shown that logic circuits are inherently resilient to variation [12,13], and the area-scaling model is excessively pessimistic.…”

Section: Introductionmentioning

confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

View full text Add to dashboard Cite

As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

show abstract

A statistical approach for full-chip gate-oxide reliability analysis

Cited by 18 publications

References 14 publications

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

Scalable methods for the analysis and optimization of gate oxide breakdown

What happens when circuits grow old: Aging issues in CMOS design

Contact Info

Product

Resources

About